Research On The Key Techniques Of High-Speed And High-Resolution Data Converters

As a bridge of the analog world and the digital signal processing,data convert-ers play an important role in the signal chain.High-speed and high-resolution data converters are not only used in modern communication systems and high-end instru-ments,but also widely used in the development of the weapon equipments,such as electronic warfare systems and phased array radar.With the scaling of the character-istic size of integrated circuits,the intrinsic gain of transistors decreases,which makes the design of analog circuits more and more difficult.However,the energy efficiency of digital circuits becomes higher.In addition,some parameters,for example,the out-put impedance of the transistor,vary along with process,temperature and bias voltage.In order to further reduce power consumption,digital signal processing is employed to solve these non-ideal characteristics of analog circuits.Adopting this design concept,this paper develops corresponding technologies to address the challenges of compara-tor offset,sampling time skew of sample-and-hold-amplifier-less(SHA-less)pipelined analog-to-digital converters(ADCs),a large dither injection,and clock phase calibra-tion in digital-to-analog converters(DACs).Firstly,a low-power and high-speed comparator architecture and a background offset calibration method are presented in this paper.An extra path providing current for the comparator core is added,and the path is closed after the comparator completes the comparison.Besides,an extra comparison is added in the sampling phase.Based on this comparison result implying the direction of the offset,a passive integrator and an extra differential pair are utilized to compensate the comparator offset.The proposed comparator circuit,together with a 16-bit 150 MSPS ADC,is implemented in a 0.18μm CMOS technology.The measured results demonstrate the effectiveness of the proposed techniques.Secondly,a new background offset calibration technique is proposed for SHA-less pipelined ADCs.A new evaluation technique is proposed to synchronously extract the values of the comparator static offset and dynamic offset induced due to the tim-ing skew and bandwidth mismatch between the multiplying digital-to-analog converter(MDAC)and the comparator input paths in the first stage through the residue output at decision points.In this work,the new calibration method is validated using behavioral models.The effective number of bits(ENOB)is improved from 5.04 bits to 11.96 bits,while the spurious free dynamic range(SFDR)is improved by 50.7 dB from our simulation.Thanks to the background calibration,comparator offset errors exceeding the built-in redundancy of the architecture become acceptable.The proposed method relaxes comparator design requirements effectively.More importantly,the calibration can maximize the input frequency of the SHA-less pipelined ADCs.Thirdly,a new large dither injection technique is proposed for improving linearity in pipelined ADCs,without losing the dynamic range of the ADC and deteriorating the corresponding amplifier’s linearity.Analyses of a proper pipelined ADC’s archi-tecture are performed for the dither injection.Then,a 9 bit capacitive DAC with split architecture is developed to inject the dither ranging from-511/1024 to 511/1024 LSB of the first stage.To avoid the overflow of the MDAC output,the novel 6 bit complemen-tary DACs embedded in the comparator threshold generation circuit are proposed to realize comparator dither injection.Besides,the dither injection amplitude is config-urable.The proposed dither injection circuit,together with a 16-bit 150 MSPS ADC,is implemented in a 0.18μm CMOS technology.The optimum dither is the 9-bit dither,improving not only the SFDR of the small signal by at least 15 dB but also that of the large signal in other case by more than 6 dB compared to the corresponding cases without dither injection.Moreover,dither injection makes the noise floor clean.Finally,a new clock phase calibration method is presented for high-speed current-steering DACs.A serious design challenge is brought by the requirement of solving the setup/hold time violations problem between the output data from the digital clock domain and the analog clock under different process,voltage and temperature(PVT)conditions,and simultaneously maintaining high spectral purity of the analog clock in current-steering DACs.A mixed-signal system is developed to detect and correct time violations for the critical analog clock.A power-efficient,novel 4-bit flash ADC,designed mainly with a new architecture and reference adaptive generation technique while keeping overhead cost low,is proposed in this paper.The ADC and XOR phase detector form the time-to-digital converter(TDC)to detect the phase difference.The detection and correction circuit,together with a 13-bit 2.4 GHz DAC,is implement-ed in a 0.18μm CMOS technology.Measured results demonstrate the effectiveness of the proposed method.The combined clock phase calibration circuit not only im-proves yield of DACs,but also increases the maximum allowable clock frequency for high-resolution DACs,which is especially advantageous for high sampling frequency design.