Research And Design Of 10 Bits Split Successive Approximation Analog-to-digital Converter(SAR ADC)

Analog-to-digital converter(ADC)can complete the task of converting analog signals into digital signals.The analog-to-digital converter(ADC)has been widely used in the fields of sound processing,medical monitoring,industrial control,and high bandwidth communication,and it is an indispensable circuit module for modern electronic equipment.SAR ADC is widely used for its advantages of simple structure,small area and low power.At present,users have higher and higher requirements for battery life of modern electronic equipment,and reducing the power consumption of analog-to-digital converters has become a huge challenge for the integrated circuit design industry.A 10-bit,125KS/s low power SAR ADC is realized in this paper.It is mainly composed of sample-and-hold circuit,digital-to-analog conversion network,comparator,SAR logic control circuit.First of all,the top plate sampling of the capacitor can reduce the number of sampling switches,which means that the power consumption in the sampling stage is reduced;secondly,the differential structure can suppress the input common mode noise and improve the circuit performance.The sample-and-hold circuit abandons the traditional CMOS switch and adopts the bootstrap technology to keep the voltage across the gate and source of the switch tube at the power supply voltage,that is,the on-resistance of the switch tube is kept at a fixed value,thereby improving the linearity of the sample-and-hold circuit.In the design of the DAC analog-to-digital conversion network,this article chooses the Vcm-based capacitor switching sequence.Compared with the traditional capacitor switching sequence,this switching schematic can effectively reduce the energy consumption during level switching of capacitive DAC.In addition,in order to reduce the circuit area of the DAC conversion network,this design uses a split capacitive DAC.The comparator uses a two-stage dynamic comparator,which is driven by a clock signal,and does not consume quiescent current during the comparison process,thereby avoiding additional quiescent power consumption.The last step is design the SAR logic circuit and the capacitor switch drive circuit.The SAR logic circuit can control the comparator and the DAC analog-to-digital conversion network to correctly complete the conversion of each digital code.SAR ADC in this paper has been implemented with Magna Chip 13.0μm BCD process,the ADC is designed and simulated with Cadence,The simulation result data is analyzed and processed by Matlab.The result shows that when the sampling rate is 125KS/s,SAR ADC dynamic performance is that ENOB=9.22 bit,SNDR =57.26 dB,SFDR=69.84 dB.