Key Architecture Design Of Four-issue Superscalar Processor Based On RISC-Ⅴ Instruction Set

Modern high-performance CPU is an essential digital infrastructure foundations for social progress and AI large-scale data processing.The superscalar architecture is the maInstream method to improve CPU processing performance,which not only significantly improves singlecore performance but also enables cluster computing for large-scale data processing,such as machine learning,natural language processing,virtual reality,etc.This paper firstly analyzes the research status of high-performance processors at home and abroad,focusing on the application of the RISC-Ⅴ Instruction set in the field of highperformance processors,and proposes a superscalar architecture that supports four-issue.The specific research content is divided into the following three parts:(1)Chapter3 discusses the characteristics of RISC-Ⅴ Instruction set and the corresponding decoder design methods,and analyzes the compressed Instructions and memory barrier Instructions that require special decoding in the RISC-Ⅴ Instruction set.In order to support the decoding of four Instructions in the same cycle,this paper proposes a combined decoder design architecture and introduces the micro-operation concept from the x86 architecture,converting four RISC-Ⅴ Instructions into five micro-operations,and providing a detailed design for controlling and transmitting the micro-operations.(2)Based on the data path design of up to five micro-operations in a single cycle,chapter4 proposes a register-renaming method for five micro-operations and a reorder buffer design to implement the disordered execution of Instructions.A separate processing logic circuit is designed for immediate jump Instructions that affect physical register allocation and release.A merge method is introduced to reduce ROB table occupancy,and port enablement and selection control circuits for ROB are designed.The four-issue architecture reduces the percentage of ROB occupancy in the range of 0～16 by 4.9%and increases it by 5.2%in the range of 17～32,improving the utilization rate of ROB and the efficiency of out-of-order execution of the processor.(3)This paper proposes an asymmetric distributed Instruction queue design that supports four-issue superscalar architecture and a dual queue control method for four port.A feedback logic is designed to address port conflicts caused by insufficient write ports in the Instruction queue,thereby effectively reducing the number of pipeline blockages.The above design can efifectively improve the processor’s Instruction stream width,increase the clock occupation ratio of 1～3 table entries in the Instruction queue by 5%to 8%under large-scale computing programs,improve the utilization rate of execution units,and provide a feasible method for superscalar processor design in RISC-Ⅴ architecture.Finally,this paper describes the specific implementation process of the above superscalar CPU architecture verification platform,code specification check and overall unit simulation test.