Study On Asynchronous Superscalar Processor Architecture Based On RISC-VISA

With the rapid popularity of mobile devices and smart hardware,as well as the strengthening trend of intelligence,the application of embedded processor chips has extended to almost every information field.Low-power design is a key and challenging aspect of embedded processor design,closely related to the instruction set architecture,microprocessor architecture,and circuit implementation.Mainstream instruction set architectures such as ARM and X86 have mature technologies,but they are either unlicensed or the licensing fees are very expensive,which restricts the innovation and development of China’s independent chip field.In terms of microprocessor architecture,traditional scalar processors are not only inadequate for increasingly complex application scenarios but also fail to meet the requirements of high-performance computing.In terms of circuit implementation,almost all processors use clock control.With the continuous increase in circuit scale and transistor density,problems caused by clock signals,such as clock power consumption and clock skew,have become more serious.Based on the above problems,this article proposes a fully asynchronous superscalar processor architecture based on the fifth-generation Reduced Instruction Set Computer Five(RISC-V).It uses clockless delay-insensitive asynchronous circuit implementation and has a work mechanism that can be started and stopped on demand without the need for re-initialization.It can improve performance while reducing dynamic power consumption.This paper adopts the open-source RISC-V instruction set architecture,supporting the RV32 IMAC instruction set type,which can meet the requirements of most application scenarios.The control path of the overall architecture is implemented using an asynchronous circuit model based on a Click controller’s "Send-Relay-Receive" mechanism,which is driven by discrete events and avoids the problems caused by clocks while reducing power consumption.In terms of microprocessor architecture,combining superscalar key technologies with clockless asynchronous circuits,excellent modularity,and strong adaptability,a low-power,and high-performance asynchronous superscalar processing method is proposed.Based on this method,an asynchronous RISC-V superscalar processor architecture is designed,realizing the out-of-order dispatch and concurrent execution of 16 instructions.Finally,a Mesh-based on-chip network(Network on Chip,No C)intra-bus is designed and implemented based on the "Send-Relay-Receive" asynchronous circuit model,enabling efficient system interconnection between the processor cores and interface modules.The front-end design of the sub-modules is completed on the ASIC platform,and simulation verification,power consumption analysis,and area analysis are performed.Compared to existing related work,this design achieves lower power consumption while ensuring processing speed,showing potential application prospects in areas such as wearables and the Internet of Things.The architecture and implementation of fully asynchronous complex processors also provide a new development path for the localization of processors.