Research On 32-Bit RISC Processor And Design Of Interface Circuit

RISC-V instruction set has become a research hotspot in recent years because of its simplicity,flexibility,free and open-source.Based on the RV32IM instruction subset,this thesis designs a six-stage pipeline structure,dual-issue,out-of-order execution 32-bit RISC-V processor core and the corresponding ICB interface circuit,so that the processor core can transmit data with external memories.The semi-custom design method is adopted to realize the physical design in the 40nm CMOS technology.In this thesis,a dynamic branch predictor based on global history is used to improve the accuracy of branch prediction.Memory access instructions are executed in sequence,so as to simplify the circuit design,while other types of instructions are executed out of order to improve the circuit performance.The processor maps 32 general logic registers to 64 physical registers by register renaming to eliminate the data dependence,including read after write dependence and write after write dependence.Besides,Tomasulo algorithm is adopted for hardware scheduling to maximize the parallelism between instructions.The high-performance multiplier is realized by booth coding and Wallace tree structure and the array divider is pipelined,which not only balances the area,but also greatly improves the frequency of the circuit.Instructions with different execution cycles adopted different write back and submission strategies,and a submission control module is designed in the submission stage to deal with branch prediction failures,interrupts and exceptions.This thesis analyzes the requirements and clarifies the design indicators.After a series of steps including RTL design,pre-simulation,logic synthesis,back-end design and post-simulation,the integrated circuit design is completed and the final layout is generated.The simulation results show that the 32-bit RISC-V processor core designed in this paper supports RV32IM instruction subset and can transmit data with external memories through ICB interface.The operating frequency is 200MHz,the layout area is 0.2809mm~2,and the power consumption is 35.95mW,which meet the design specifications.