Research On DSP Instruction Pipeline Based On Register Rename

With the continuous development of science and technology,high-performance processors are playing an increasingly important role in daily life and the military field.In the development of processors,people have adopted various methods to improve processor performance.But so far,the most widespread approach has been to improve instruction-level parallelism.Correlation among instructions is the main factor affecting instruction-level parallelism,including data correlation,structure correlation,and control correlation.By using register renaming technology,the false data correlation between instructions can be simply and effectively eliminated,and potential parallelism between instructions can be mined,so that the pipeline can maintain a "full" state to the maximum extent,and finally achieve the purpose of improving processor performance.Based on the research of superscalar processors and the characteristics of the register renaming mechanism,this paper redesigns and optimizes the DSP instruction pipeline,improves instruction-level parallelism,and effectively reduces latency,area,and power consumption.The specific research work is as follows:1.Design of register renaming mechanism.According to the structure of the digital signal processor under study,the register is renamed using a unified PRF,and the main modules of the register rename mechanism are discussed in detail.Using the renaming mapping table and free list,the renaming process is divided into three parts: reading source registers,allocating rename registers,and updating instruction registers.2.Optimization of DSP instruction pipeline.The size of the physical register file and the number of read and write ports determine the access time of the register file.Based on the shortcomings in the management and use of physical register resources and renaming logic,an optimized design was carried out.Aiming at the problem of wasteful use of physical resources,the reuse technology of physical registers is designed,and the allocation of physical registers is postponed until the result is actually occupied,which greatly reduces the number of physical registers and the occupied time.Aiming at the problem of low port utilization of the rename mapping table,reduce the number of source operand read ports and optimize the control logic to improve the area and access speed of the rename logic.3.Evaluation of DSP instruction pipeline.The simple program and the SPEC CPU 2000 integer benchmark program were tested under the soft environment and the Simplie Scalar simulator,respectively.Then analyze the experimental results and evaluate the processor performance to determine the final register renaming scheme.Use Verilog HDL language to complete the design of related modules,and use tools such as Design Complier to synthesize,compare the delay,power consumption and area before and after the rename mechanism improvement.The experimental results prove that the design can reduce the delay time by 8.5%,the power consumption by 39.8% and the area by 65.3% when the IPC loss of pipeline is less than 5%.This means that while reducing the number of physical registers and reducing design complexity,greater frequency and instruction parallelism can be achieved,thereby improving the performance of the processor.