RISC Architecture Based Processor Design And RTL-Level Implementation

Processor design and implementation, which is a high-complexity and high-tech core technology, has been only mastered by a few companies and laboratories in a handful of countries. In such a context, it appears significant that exploring and summarizing a set of reasonable scheme about processor design and implementation. And this paper is an attempt to complete such a work.In this paper, with the study of a design scheme about a 32-bit RISC based processor, I give a pipeline design scheme through analyzing the instruction set and reverse reasoning. Then, solve the structure relativity, data relativity and control relativity introduced by the pipeline and give a design of cache and TLB to achieve the aim of completing the memory accessing within one CPU cycle. Then through adjusting the design of modules of forepart(such as PC, branch-prediction, instruction-fetch and instruction-decode...) and introducing several modules(such as reg-mapping, reorder-queue, branch-queue, issue-queue and so on) to the design , I advance the design to the superscalar-stage, and also give a design diagram of superscalar. Entire design process is guided by following principle: from simple to complex, functional modules increasing gradually and gradually refined.On this basis, the thesis put forward a RTL implementation scheme of a 32 bits RISC CPU, which includes the details about implementation of memory module, the details of every part in the module of CPU, as well as the details of mutual cooperation between the memory and the CPU module.At last, I introduce some new technologies and ideologies which includes multi-core, multi-thread and also the calculation of 64 bits in the designing field of the modern processors, to be used to study and for reference.