Design And Optimization Of The Register Renaming Mechanism In An Out-Of-Order Superscalar Processor

With the development of the science and technology, the processor has been used more and more widely. Meantime, the performance requirement of applications for the processor is increasing. The main way to improve the performance of the processor includes:increasing the frequency of the processor and improving the instruction level parallelism. Now, improving the performance of the processor by increasing the frequency is becoming more and more difficult, and to improve the instruction level parallelism becomes the main way. The main reason to limit instructions running in parallel is the dependencies between instructions, including the data dependency, the control dependency and the name dependency. Register renaming can improve the performance of the processor by removing false data dependencies and exploiting instruction level parallelisms while maintaining true data dependencies. Based on studying of the related work of the register renaming techniques, we designed a register renaming mechanism for the out-of-order superscalar processor developed by our team, and optimized it according to the performance analysis. The main contributions are as follows:1. Designed of the register renaming mechanism. According to the microarchitecture of the out-of-order superscalar processor, a register renaming mechanism is designed. This mechanism is based on the rename buffer; that is to say, there is a separate rename register file for renaming. All types of architecture registers shared this rename register file and rename map tables record the mapping relationship between the architectural register and the rename register.2. Optimization of the register renaming mechanism. The performance of the processor is analyzed by using the performance counters. It is found that instruction renaming is stalled frequently due to lack of rename registers, and for CFP2000 programs, it is more serious. According to the analysis, the number of rename registers is increased to improve the performance of the processor, and we implemented it using Verilog, in which the number of rename registers can be configured. Added rename registers will inevitably increase the area of the rename register file. In fact, the area of the register file is big originally due to so many read ports. In order to optimized the area, a method of read ports sharing is proposed to reduce the ports of register files. This method can reduce the area of register files with the impact on the performance as small as impossible.3. Functional verification of the register renaming mechanism. The register renaming mechanism and its optimization implementation are verified by various methods of functional verification. According to the characteristics of the register renaming codes, different verification method is used for different functional modules to improve the efficiency of the verification.4. Evaluation of the register renaming mechanism. The register renaming mechanism and its optimization implementation are evaluated from the performance and the physical implementation. Thus, the design can be measured from performance, area and timing, which is helpful to determine the final implementation of the register renaming mechanism in the out-of-order superscalar processor.