Design And Verification Of Superscalar Processor Core Based On RISC-Ⅴ Instruction Architecture

With the rapid development of the field of processor technology,RISC-Ⅴ has gained popularity.Turing Prize winner David Patterson said,"In three to five years,RISC-Ⅴ chips will be everywhere!".Considering that entering the high-performance field is an important sign of chip architecture going towards the mainstream and that the open source instruction set RISC-Ⅴ has gradually become the object of embrace in the industry due to its outstanding characteristics,combining RISC-Ⅴ instruction set and superscalar technology,developing a high-performance processor core has important value and significance.Based on this background,in this thesis,based on the RSIC-V architecture,a relatively 4-way disordered execution superscalar processor core running in machine mode with certain performance,named Mashiro,has been completely implemented.The processor has a 11-level pipeline depth and is divided into four sub-system,the instruction unit IU,the execution unit XU,the memory access unit LSU and control unit CTRL.It supports the RV64 IM instruction set and Zicsr.In the IU section,a decoupled non-blocking front-end is used,with a 32 KB,2-way Instruction-Cache added to reduce suspension caused by fetching.Combining a static branch predictor based on pre decoding with a dynamic branch predictor based on Gshare and TAGE to improve the branch prediction accuracy.In the XU section,the Issue-Queue adopts a unified issue method based on agematrix;It has four execution units,including two ALUs,one AGU,and one BRU module.SRT16 algorithm is used for division and ordinary Booth algorithm is used for multiplication.The XU also has 64 physical registers to solve pseudo-correlative problems,as well as a ROB to restore the program order of instructions.In the LSU section,a non-blocking memory access pipeline is designed using the Load and Store Queues with a depth of 16 to reduce the suspension delay caused by memory access.This section also has a 64 KB,4-way Data-Cache,which is replaced by PLRU,and also has matching refill-units and a Pipe-Line.In the CTRL section,it solved the pipeline refresh problem caused by exceptions and interrupts,and implemented relevant CSR registers.The XU section can read and write CSRs too.This thesis uses Verilog HDL language to design and implement the processor core,and in order to better achieve the verification goal,this thesis designs a simple SoC system with UART transmission function,clock interrupt function,and display function.Then,it builds a RISC-Ⅴ compilation environment,and writes C programs and library functions to verify the processor’s function.The verification results show that the processor core can achieve the expected goal.Finally,the processor is synthesized using130 nm,and the result shows that the maximum operating frequency of the processor core is 125 MHz.