Research On High Performance Embedded Risc-Based Processor

Rapid improvement of chip design techniques and the deep-submicron technology has driven the embedded system design into System-On-Chip (SoC) age. The author of this thesis attended the project supported by National 863 Program and the development of a media SoC namely MediaSoC3221A, which is designed by the SoC R&D Group of Zhejiang University. This thesis focuses on the R&D of an embedded RISC-based processor, which is integrated into MediaSoC3221A as one of two programmable processors. The main contents and innovative points of this thesis can be summarized as follows:RISC-based processors have extended themselves into all kinds of embedded applications. Because different application has different features, it requires different processors. For example, the multi-thread or multi-core processors processing applications with plenty of thread-level parallelism are preferable;inversely, single-thread application can benefit more from a high performance multi-issue processor. According to consideration above, we have designed a new processor RISC3202 based on two RISC3200. RISC3202 has the mix micro-architecture of dual-issue and dual-core and supports the same instruction set architecture (ISA) with RISC3200. It can work on both dual-core mode and dual-issue single processor mode, which is an innovation in processor micro-architecture design.Multimedia application is one of the main driving forces for processor design and becomes one of the main workloads of RISC-based processors. Because the traditional RISC-based processors are not optimized for this type of application, they have low efficiency in processing multimedia applications. Therefore, an effective method is to extend its ISA for multimedia processing. In this paper, focusing the drawback of MDS-I extension of RISC3200's ISA, which has powerful media data processing ability but awkward media data providing ability, we have extended the MDS-I1 for high efficiency media data provision. The experiments show MDS enhance RISC3200's multimedia processing ability in large degrees.In order to improve the efficiency and the quality of program generation for processor functional verification, the pseudo-random generation method is studied in this paper, which is comprised of the single instruction generation model and the program template. The instruction generation model is used to guarantee the legality and effectiveness of generated instruction, and the focus of generated instruction sequences is guaranteed by program templates. With the help of this method, function verification programs are developed conveniently in C language.How to optimize embedded software is a key problem during SOC development. This paper gives a specific software optimization example, the MP3 decoding program on RISC3200. On the basis of above work, we propose general software optimization techniques for embedded systems, which are applied to optimize our MP3 decoder on RISC3200. At last, we propose partitioning the MP3 decoding program into two threads which are executed parallelly on RlSC3202's dual-core mode, and MP3 decoding program achieves 1.78 speedups on RISC3202.