Design Of 32-bit RISC Processor Core Based On 40nm CMOS Process

Because the RISC processor's instruction set,the decoder and the control circuit are simple,it is easy to achieve high frequency.Thus,it is widely used in high-performance servers.MIPS is the most streamlined and pure RISC processor.This article improves the traditional five-level pipeline MIPS32 processor from the aspects of improving the data path ALU performance and using dynamic scheduling multiple transmissions to achieve instruction-level parallelism.The RISC processor that executes functions out of order,and adopts a semi-custom design method,realizes the physical design under the TSMC 40nm CMOS process.This article introduces the design method of high-performance ALU.The algorithm is implemented in gate-level circuits through Verilog HDL data flow level description,instead of automatic optimization of logic synthesis tools.On the basis of balancing area-speed,the path delay is minimized.ALU of full combination logic.The high-speed ALU circuit in this design includes a log shifter,a super-forward carry adder using the Breng-Kung parallel prefix carry tree,a Wallace tree parallel multiplier using Booth coding,and an array divider.In this disseration,a 2-bit saturation count branch predictor is used to reduce the control risk,and the controller is designed for the directly mapped Cache.There are three ALU modules and one AGU module in this design.Each clock cycle can execute up to three arithmetic logic instructions and one access instruction at the same time.The processor maps 32 general logical registers to 128 physical registers by renaming the mapping table and reordering the cache,and then dispatches them to 4 independent compressed transmit queues.The launch queue controller dynamically schedules the pipeline through the tomasulo algorithm,sends instructions that have no correlation to the execution unit,and finally uses the reordering cache to restore the normal order of instructions.The RISC processor designed in this paper implements MIPS32 commonly used integer instructions with a running clock frequency of 166MHz and a layout area of 0.312mm~2.It uses separate memory for data and instructions,and each has a direct mapping cache of 1KB.This design has a 7-stage pipeline,reads and emits 4instructions per cycle,and is executing out of order.This article analyzes the requirements,clarifies the design indicators,and completes the design according to the integrated circuit design process,through RTL design,circuit design,verification platform construction,pre-simulation,logic synthesis,back-end design and verification and other steps.After simulation verification,the function and layout meet the design specifications and meet the design requirements.