Research On Nanoscale High Performance Noise Shaping Analog-to-Digital Converter Architecture And Circuit

As a key medium to connect the analog and digital worlds,analog-to-digital converters expands the variety of application scenarios with the development of wireless communication systems in the forthcoming technological generation.There is an increasing demand in the market.In the field of 5G communication,the requirement for ADC performance is increasing.New architectures are urgently needed.Combined with noise-shaping SAR ADC and pipelined architecture,the successive approximation register(SAR)-assisted noise-shaping(NS)pipelined architecture(Pipelined-NS-SAR)is presented,which can achieve low power consumption,high resolution and high speed,thus leading to a hot research direction for high-performance ADCs.It is appreciable to make a research on Pipelined-NS-SAR ADCs.This thesis introduces the technical principle,basic architecture and key modules of Pipelined-NS-SAR ADCs.Firstly,the techniques for achieving noise shaping are introduced.Besides,two common types to achieve noise shaping,cascode integrator feed-forward(CIFF)and error-feedback(EF)noise-shaping ADCs,are discussed and comparatively analyzed.Then the basic architecture and the operating principle of the conventional two-staged Pipelined-NS-SAR ADCs are analyzed.Based on that,the architecture of the capacitor interleaved Pipelined-NS-SAR ADC is introduced from the system-level perspective.Besides,a Pipelined-NS-SAR ADC architecture based on capacitor multiplexing technology is proposed.Compared with the architecture of capacitor interleaved Pipelined-NS-SAR ADCs,the architecture of Pipelined-NS-SAR ADCs based on capacitor multiplexing technology multiplexes the feedback capacitor as the reference voltage attenuator for the sub-ADC,which serves as a medium to implement the residue feedback,thus resulting in a standard first-order noise transfer function(NTF)without extra active circuits,which achieves a great area saving,power efficiency as well as design simplicity.Additionally,the thesis analyzes the principle of ADC redundancy calibration technique,illustrating the underlying principle of misalignment stacking.Then,from the module-level perspective,the circuit structure and operating principle of key modules such as sample-and-hold circuits,comparators and interstage operational amplifiers are introduced in detail,the non-ideal effects of which are also analyzed.Finally,fabricated in a TSMC 65 nm CMOS process,a 13-bit 200 MS/s Pipelined-NS-SAR ADC with capacitive multiplexed techonology is achieved.The protype adopts a "6+5" two-stage pipelined structure with redundancy calibration techniques.Several techniques are adopted to achieve performance improvement.Among them,the inter-stage gain halving technology achieves a reduction in the gain requirements of the MDAC and the quantization range of the sub-ADC,thus leading to an improvement of energy efficiency.The capacitive multiplexed switched-capacitor technique configures the feedback capacitor of the switched capacitor amplifier as an integrated capacitor to achieve residue summation in the amplification phase,thus achieving a full-cycle delay required in the EF structure with first-order noise shaping.Meanwhile,the feedback capacitor of the switched-capacitor amplifier is configured as a reference voltage attenuator for sub-ADC,which avoids introducing extra attenuation capacitors with large area and achieves high linearity performance.In addition,a bootstrapped switch with improved gate voltage is presented,achieving an improvement in the linearity through reasonably biasing the substrate potential of the switch MOS while improving the sampling speed through minimizing the delay on the switch transistor.The two-staged fully dynamic comparator structure optimizes the operating speed and avoids static power generation.The post-layout simulation results show that the prototype achieves a signal-to-noise-and-distortion(SNDR)of 78.9d B and a spurious-free-dynamic-range(SFDR)of 91.3d B at 200MS/s with oversampling ratio(OSR)of 8.The ADC exhibits an ENOB of 12.81 bit and the total power consumption is 3.96 m W.