Research On Hardened Latch Designs For Multiple-node Upset In Integrated Circuits

With the advancement of semiconductor manufacturing technology,the size of transistors has reduced rapidly,and researchers have successfully developed larger integrated circuits with less power consumption and area overhead.However,modern integrated circuits are increasingly vulnerable to high-energy particle impact,which causes soft errors.These high-energy particles strike the sensitive nodes of the integrated circuit,causing single-node upset.However,due to technological development,the distance between transistors is getting closer and closer.The impact of high-energy particles may simultaneously change the logic state of two or three nodes,resulting in double-node upset or even triple-node upset.The radiation hardness structure for single-node upset can no longer meet the current demand.Therefore,it is essential to design latches that tolerate multiple-node upset.Aiming at the latch in the radiation environment is prone to soft errors,resulting in a single event upset.At the same time,some latches have a high cost and low reliability.Based on clock-gating(CG)technology and high-speed transmission path technology,this paper proposed two kinds of triple-node upset tolerant latches,the main contents are as follows:1.First,this paper proposes a triple-node upset tolerate hardened-latch(LTNUHL)design.The LTNUHL latch consists of two single-node upset self-recovery modules(module1,module2)and one two-stage error interception module.Each single-node upset self-recovery module is connected with three C-elements and two inverters to complete data storage and loop feedback.The two-level error interception module uses two 2-input C-elements to constitute the first-level error interception.It then uses one CG-based 2-input C-elements to form the second-level error interception alone.The simulation results show that the LTNUHL latch can tolerate any triple-node upset;the delay and power consumption are reduced by 68.68% and 68.86%,when the area is only increased by 2.00%.2.To improve the performance of the LTNUHL latch can’t self-recovery,a triplenode upset self-recovery latch(HTNURL)design is proposed.The HTNURL latch mainly consists of four C-elements modules in series.Each module consists of four 2-input C-elements.The outputs of each 2-input C-elements connect the inputs of the two 2-input C-elements specified in the following modules.In contrast,each input of the 2-input C-elements comes from the two 2-input C-elements defined in the previous modules.The final C-elements module uses four CG-based 2-input Celements to reduce the power consumption of the latch.Simulation results show that the HTNURL latch has triple-node upset self-recover ability,the delay and power consumption are reduced by 60.55% and 51.45% when the area increases by 27.50%.Figure [29] Table [7] Reference [68]...