Research And Design Of Phase-Locked Loop Circuit Based On 55 Nm Process

Phase-Locked Loop(PLL)is one of the key modules in transceivers.It not only provides a local oscillator signal for the modulation and demodulation of communication signals,but also provides an accurate clock for the correct operation of information in digital circuits.Therefore,PLL has always been the focus in the design and research of analog integrated circuits.It occupies a pivotal position.Among all the performance indicators of PLL,phase noise,spurs,power consumption,cost and tuning range are the main concerns of researchers.Due to the rise of the Internet of Things and the increasing demand for consumer electronics,PLL faces problems such as different application requirements,high complexity,and noise performance to be optimized.In this thesis,a PLL used in 433 MHz voice chip is presented.For this target application,it has the advantages of small area,low phase noise,low power consumption,etc.Firstly,this thesis introduces the development history and classification of phase-locked loops,and summarizes the research status from the products released by integrated circuit design companies and the research results of domestic and foreign universities.Then the working principle,basic architecture,main modules and performance indicators of the PLL are proposed.Secondly,the s domain model is employed to analyze the noise transfer function of each module.The noise suppression methods from the aspects of noise source generation and noise transfer function are discussed.Matlab is used to verify the noise contribution of each module.According to the specific application,a ring oscillator using PMOS for cross-coupling,a frequency divider with a MASH 1-1-1 structure differential integral modulator,a three-state gate frequency discriminator and a current phase discriminator are selected.A method of adding positive temperature coefficient resistors for temperature compensation is proposed.Through reasonable design parameters,the trade-off and optimization of PLL noise,area and power consumption are accomplished.Finally,the layout is drawn,the parasitic parameters are extracted by PEX,and the post-layout simulation of each module and the overall loop of the phase-locked loop is carried out.The design is fabricated using UMC 55 nm CMOS process with 1.2 V supply voltage at 433.92 MHz.Tested results shows the area of PLL is 0.041 mm2.The circuit consumes about 4.7 mW and the phase noise is-102.58 dBc/Hz@1MHz.