FD-SOI Low Phase Noise And Fast Locking Time Phase-Locked Loop Design

In recent years,5G communication has become the mainstream wireless communication technology due to its wide bandwidth,fast transmission speed,low latency,and high mobility.The dense information transmission of 5G wireless networks requires higher frequency and phase noise performance from clocks.Compared to other frequency generation circuits,a phase-locked loop has advantages such as a wider tuning range,higher center frequency,and lower phase noise.Therefore,this paper focuses on the design of a high-performance charge-pump phase-locked loop in the context of the continuously increasing clock performance requirements in 5G wireless communication.This article first studies the theory of phase noise of oscillators under the silicon-on-insulator(SOI)process,analyzes the mechanism of phase noise generation,and improves the oscillator from both structural and process aspects.In the traditional structure,the tail current source is removed to increase the output voltage amplitude and reduce the impact of tail current source flicker noise on the oscillator.A tailless current-source cross-coupled delay cell structure is used to speed up the level conversion time of the oscillator and reduce the influence of noise current on the oscillator.The FD-SOI process is used for circuit design in the process aspect to reduce substrate noise by utilizing the feature of full isolation of FD-SOI and optimize the phase noise level of the oscillator by using anti-well devices to lower the threshold voltage.Secondly,this article optimizes the structure of the charge pump and proposes a new charge pump structure that matches the charging and discharging current over the full voltage range by combining the characteristics of differential input with low common-mode noise of the current steering charge pump and the advantages of high output impedance and high charge-discharge current matching of the output impedance-enhanced charge pump.Finally,based on the Global Foundries 22nm FD-SOI process,the phase noise level of the voltage-controlled oscillator in the phase-locked loop circuit designed in this article was-99.79d Bc/Hz@1MHz,and the current mismatch of the charge pump was less than 1%with a charging and discharging current of 100μA.Then,the layout of the designed phase-locked loop circuit was drawn,and the parasitic parameter extraction of the overall layout was performed for post-simulation.The simulation results showed that the lock-in time of the phase-locked loop was 3μs,the total power consumption was less than 16m W,the phase noise level was-98.8d Bc/Hz@1MHz,and the overall layout area was 0.14mm~2.