CMOS Phase-locked Loop Circuit For The JESD204B Interface

With the development of information technology, the speed of information dissemination and processing has been greatly improved, which needs higher frequency converters and processors. Therefore, the high speed interface circuits to support higher speed converters has become urgent new issues in integrated circuit design world wide. In China, almost all of the high-speed high-precision data converter interfaces are imported from Europe and the United States, so designing high-speed converter interface circuits has become a domestic industry and academia research focus. China relatively fall behind in the field of high-speed precision interface. However, with the improvement of China's national defense, communications, competition in this area has already begun heating up. So our urgent to carry out research and development of high-speed interface chip key technologies for the early developed with independent intellectual property rights, which is very important in protection of national security and enhance the core competitiveness of electronic products. The traditional parallel interface can't meet the needs of the development of the converter. Therefore, the serial interface circuits based on JESD204 B standard are used in recent years, which can help to improve the transmission rate, reduce the number of the pins. Moreover,it is easy to expand and more and more converter suppliers, FPGA manufacturers adopted this standard. So it is expected to become the future protocol standards for converter interface. As the source of the local clock, the phase lock loop has some important influence on the performance of the interface circuits, such as the transmission rate and the bit error rate. Charge pump PLL is widely used in circuit designed for JESD204 B due to its advantages of small lock phase error and unlimited capture bandwidth.In this paper, a design scheme of CMOS phase locked loop circuit for transmitter clock is proposed, and the circuit implementation scheme of the bandgap reference, the phase frequency detector, the charge pump and the ring differential VCO are presented.Firstly, the basic structure of the charge pump phase locked loop and the linear model of the system are introduced in chapter two. Then,the noise concept is illustrated by analyzing two common used VCO models in chapter three. According to the design requirements of JESD204 B interface circuit, a CMOS phase locked loop circuit design scheme is proposed in chapter four, which is based on the ring VCO phase locked loop circuit. Finally, the whole circuit is simulated based on 65 nm TSMC process in chapter five. The simulation results show that the PLL lock time is 150 ns at the room temperature of 27 degrees(process TT), and the phase noise of-103 dB has been achieved at the output frequency of 5GHz and the offset frequency of 10 MHz. The simulation results show that the VCO oscillation center frequency is 5.15 GHz.Moreover, a gain range of 11.2GHz/V to 13.3GHz/V, a large output frequency range of 2.1-7.8GHz and a phase noise of-83.7dBc/Hz(at 1MHz frequency offset)are achieved, respectively.