Research And Design Of Fractional-N Ring VCO Phase-locked Loop

Phase-locked loop(PLL)circuit is one of the key modules in modern wireless communication system.It generates local oscillation signal for the modulation and demodulation of the system.In addition,PLL plays an important role in frequency synthesizer,reference clock and clock extraction.Therefore,PLL has been a hot research topic for a long time.Among all those PLL performance parameters,phase noise,tuning range,area and power consumption etc.are of special interest for researchers.Due to the wide application of consumer electronics,frequency synthesizers with low power and low cost are widely used.An example is using the 433MHz ISM band wireless technology to trans it data.In this thesis,a phase-locked loop with low power consumption and low cost is presented.Firstly,current research status of PLL is given.Topology,working principle,classification and performance of PLL modules are analyzed.Secondly,the s domain model of PLL is employed to analyze the phase noise of PLL.Simulink tool is used to build the functional model of PLL in Matlab to verify the noise contribution of each module.Then,a cross-coupled PMOS ring oscillator,a fractional-N divider with Delta-Sigma modulator of MASH1-1-1 structure and the low-mismatch current steering charge pump are chosen according to the application requirements.A method of resistance temperature compensation and a circuit of low current mismatch are presented.Layout techniques are used to guarantee desired performances of the PLL.Finally the chip is tested and measurement results are provided.The design is fabricated using TSMC 0.18μm RF CMOS process.Tested results show that the phase noise at 433.92MHz frequency is-100.36dBc/Hz@1MHz.The whole circuit consumes about 6.84mW with 1.8V supply voltage and the tuning range is 260MHz-880MHz.