Design Of Clock And Data Recovery Circuits For 400G Optical Interconnection Chip

With the rapid development of artificial intelligence and machine learning technologies,the need for large-scale data centers is becoming more and more urgent.These data centers need to process large amounts of data and perform complex computation and analysis,thus requiring efficient computational resources and large storage capacity.To improve computational efficiency and resource utilization,data centers usually allocate resources such as computation,memory and storage into different resource pools for resource sharing and optimization.High-bandwidth,lowlatency and low-power interconnect technologies are also a very important part of the data center.Communication between servers,storage devices and network devices in a data center needs to be fast and reliable to ensure efficient data transfer and processing.Therefore,technologies such as high-speed optical interconnects are widely used in data centers to meet the needs of high-performance computing and large-scale data processing.In this paper,the key technologies of Clock and Data Recovery(CDR)circuit for 400G application rate scenario are investigated,and the transmitter CDR circuit and receiver CDR circuit are designed and implemented in 28nm CMOS process and 45nm SOI(Silicon-On-Insulator)CMOS process,respectively.The design and implementation of the transmitter CDR circuit and receiver CDR circuit were completed in 28nm CMOS process and 45nm SOI(Silicon-On-Insulator)CMOS process respectively.The CDR circuit arrays for 400G optical transceiver requirements are composed in the form of 8 channels.A clock and data recovery circuit with a single-channel data rate of 56Gbps for 400G optical communication receivers was designed using a 45nm SOI CMOS process.The improved digital phase interpolator CDR architecture proposed above is used to form an 8-channel architecture,and the quarter-rate baud rate sampling is realized using the integral phase discrimination technique,the input data encoding is NRZ code type,the chip area is 855 μm × 432μm,and the power consumption is about 300 mW.The clock phase noise is-92.34 dB/Hz@100KHz and-115.22dB/Hz@1MHz 和125.84dB/Hz@10MHz,respectively,and it is able to enter the locked state within 400 ns.A clock and data recovery circuit with a single channel data rate of 56Gbps is designed for 400G optical communication transmitters using a 28nm CMOS process.The proposed improved digital phase interpolator CDR architecture is also used to form the 8-channel architecture,and the data conversion selection technique is used to realize one-half rate 2-fold oversampling,the input data encoding is PAM4 code type,the chip area is 571 μm × 190 μm,the power consumption is about 280 mW,and the peak-topeak jitter of the recovered data is 945fs,the peak-to-peak jitter of the recovered clock is 760fs,the clock phase noise is-102.34dB/Hz@100KHz,-118.9dB/Hz@1MHz和124.15dB/Hz@10MHz,respectively,and it is able to enter the locked state within 300 ns.