Research On Clock Data Recovery Circuits In Optical Communications

Wireline communication has doubled the data rate every 3-4 years over the last two decades,due to increasing demand in high-performance computing,and most recently from machine learning and AI.With the increase of data transmission rate,the shortcomings of coaxial cable in the high-speed transmission appear,such as high loss,low density and high power consumption.Compared with metal,optical fiber is in terms of its high density,low loss and low power consumption.Therefore,optical fiber communication is likely to become an important way to solve the bottleneck of high-speed communication.Optical communication system is mainly composed of electro-optical transmitter and photoelectric receiver.The photoelectric receiver is composed of a photodiode,transimpedance amplifier,limiting amplifier,clock and data recovery circuit and output driver.The CDR is the core circuit of the electronic-optical receiver.It determines the performance of the receiver,which means it is irreplaceable.The function of CDR circuits in the system is to recover the correct sampling clock from the input data and resample the data to reduce the input jitter.As the data transmission rate increases,the operating rate of the CDR circuits is also continuously increasing.A high-speed clock signal requires a drive circuit with a strong drive capability to ensure the quality of the clock signal,thereby reducing the jitter of the clock and data,but it also generates huge power consumption.How to achieve low power consumption while ensuring low jitter data is a research hotspot in CDR circuits.In view of the two requirements of low jitter and low power consumption,this thesis investigates and analyzes the circuit architecture of the CDR circuit,the sampling method and the modulation code type of the input data.A 56Gb/s clock data recovery circuit with baud rate sampling is implemented in 45 nm SOI CMOS process.The chip has low power consumption while achieving high data rate.The area of this chip is 1200um*770um,the peakto-peak jitter of the recovered data is 3.12 ps,the peak-to-peak jitter of the recovered clock is2.22 ps,and the power consumption is 201 m W.Thesis work includes:(1)The continuous-time linear equalization circuit is used to equalize the input signal,which compensates the high-frequency loss of the signal and improves the integrity of the signal;the series and parallel inductance peaking technology is used to expand the bandwidth of the analog front-end module to 35.3GHz,which can meet the requirements of 56 Gb /s data rate transmission requirements.(2)A quarter-rate phase detection structure is adopted,which reduces the operating frequency of the clock logic link,and reduces the power consumption of the clock drive circuit and clock logic circuit;the sampling method of baud rate sampling is adopted,and the sampling method is implemented by means of integration.circuit.Compared with oversampling,the baud rate sampling reduces the clock phase requirement by half,which greatly reduces the power consumption of the clock data recovery circuit while ensuring the correct sampling.(3)According to the designed phase interpolation CDR circuit,the corresponding zdomain mathematical model is established,and the loop characteristics of the mathematical model are simulated on Matlab software.The CDR loop indicators under different loop parameters are obtained through simulation,and the appropriate loop parameters are selected according to the requirements.(4)According to the design requirements,define the indicators and interfaces of each module in the CDR system.Complete the schematic and layout design of each module,improve the overall layout of the CDR circuit,and add test auxiliary circuits.Design the chip pads and the overall power lines of the chip,and tape out in November 2021.