Design And Implementation Of MIPI D-PHY Physical Layer Digital System

As smartphones and other multimedia become more popular,consumer demand for multimedia features on mobile devices has increased,and this trend has driven device manufacturers to integrate more advanced peripherals in their designs,such as megapixel phones and a higher resolution screen.Integrating these capabilities into mobile devices presents new challenges to the industry in terms of power consumption,performance,time to market,and overall system cost.In 2003,well-known semiconductor companies such as ARM,Nokia,ST,and TI jointly established the Mobile Industry Processor Interface(MIPI)Alliance.The MIPI protocol is proposed to address the contradiction between the high bandwidth requirements of the growing high-definition image(video)transmission and the low rate of traditional interfaces,thereby shortening the product development cycle and enhancing the compatibility of interface products between different vendors.D-PHY,M-PHY,and C-PHY are the three common physical layer interface standards developed by the MIPI PHY working group,with the most widely used in the field of cameras and display devices based on the D-PHY physical layer.In this thesis,the D-PHY v2.1 protocol specification is deeply researched and analyzed.The D-PHY working modes are analyzed,supports a configurable master-slave mode,highspeed transmission mode,Escape mode and Reverse mode,high-speed transmission data rate of 2.5Gbps,low-speed transmission rate of 10M/s high-speed serial interface.The design focus of this thesis is mainly divided into two parts:physical coding sublayer subsystem and BangBang all digital phase locked loop subsystem.The thesis elaborates the working principle and design idea of the D-PHY physical coding sublayer,and gives a detailed physical coding sublayer architecture diagram,which completes the key modules including the transmit and receive state machine module,the 8b9 b codec module and the Sync_Coma lock detection module.Design and propose a built-in self-test design for high-speed interface testing;The working principle and design idea of the all digital phase-locked loop based on Bang-Bang structure are expounded in detail.An improved all-digital phase-locked loop of Bang-Bang structure is proposed.The simulation model of Simulink system is built and the Bang-Bang complete The digital phase-locked loop subsystem is designed to complete key module design including Bang-Bang phase detector,automatic frequency control module,digital filter module,lock monitor module and numerical control oscillator module.In this thesis,the PMA simulation model is built.In the Synopsys VCS and Candence spectre-verilog simulation environment,the key sub-modules in the system are simulated and verified.Three loopback paths are built for built-in self-test verification and the overall D-PHY is simulated,verified the analysised.At the same time,the synthesis and timing analysis of the design are completed,and the corresponding pre-simulation,post-simulation and hybrid simulation are performed on the netlist file.The simulation results show that the working modes of the D-PHY physical layer digital system designed in this thesis are correct and meet the requirements of the protocol.The Bang-Bang digital phase-locked loop can be oscillated and can correctly lock the frequency.