| With the popularity of various smart display devices,people’s requirements for display performance are also getting higher and higher,and high resolution has become a development trend.In order to meet this development demand,there are also more stringent requirements for display technology.In the application field of display technology,some traditional display interfaces such as RGB＿TTL and LVDS have their own shortcomings in terms of high-speed data transmission and reduced power consumption,which cannot meet the needs of high-definition display.This paper studies and designs a MIPI DSI interface for LCD display driver,which is a serial display interface based on the MIPI Alliance specification.It is compatible with the transmission of video data and instruction data compared with the traditional display interface.At the same time,it improves the transmission speed of data and reduces the transmission power consumption.This article first introduces the MIPI DSI interface protocol,and then proposes a solution for the MIPI DSI display interface in the design of LCD display driver.It can support data transmission with a resolution of 1080p and a frame rate of 60fps.According to the requirements of the interface protocol and specifications,the design architecture of the MIPI DSI interface is established.There are three modes of operation in the interface circuit,each of which transmits different information to the display module.The MIPI DSI interface circuit studied in my article consists of four layers of circuits,including the physical layer,the channel management layer,the protocol layer,and the application layer.The physical layer circuit receives the serial video data sent by the host in high-speed mode and converts it.It receives the instruction data in low power mode with the function of reverse transmission.Through the serial processing method,the transmission speed is improved.The channel management layer circuit distributes and fuses the data according to the number of channels configured,so that it is transmitted in the protocol order.The protocol layer circuit codes and decodes the packets in the path,and at the same time,it adds the functions of ECC check and CRC check to the packets in the transmission process,and processes the data errors in the transmission,which improves the accuracy of the data transmission.The application layer circuit converts the DSI format into DBI or DPI format data output.The DPI interface transmits video data to the display module,and the DBI interface transmits control commands to the corresponding registers in the display module.The configuration is initialized by reading and writing the internal registers of the interface circuit by the I~2C module.The improvement of this design is that the clock generated by internal XOR processing is used in low-power mode to receive data,and it is in an invalid state when the host does not send data,improving the accuracy of receiving data.In CRC checking,serial can be improved to parallel processing to avoid the impact of using a high-frequency clock on system stability.Simulation verification ensures that the functional points and timing of the interface circuit meet the expected requirements,and the DSI interface adopts the TSMC 90nm process for logical synthesis and formal verification,which further ensures that a correct netlist is provided for the back-end design.The combined area is 93700.860μm~2,the static power consumption is 0.325m W,and the dynamic power consumption is 3.084m W,there is no violation in timing,which meets the design requirements,and the transmission rate of a single channel can reach the theoretical value of 811.01Mbps when transmitting image data of 1080p/60fps. |
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