Research And Design High Performance CMOS Pipeline ADC

Analog to Digital converter(ADC)is an essential device for converting Analog signals into Digital signals.In recent years,the rapid development of wireless communication technology and digital signal processing technology has put forward high performance requirements for ADC.At the same time,with the development of CMOS technology,ADC design is also facing more and more challenges.Among commonly used ADC types,Pipeline ADC has a good compromise in performance parameters such as accuracy,speed and power consumption,and has become the main architecture of choice for high-speed and high-resolution ADC research at home and abroad.Design of a 12 bit 25MSPS Pipeline ADC based on TSMC 180 nm CMOS process is discussed in this thesis.The basic principle of ADC is first introduced,then the whole architecture is analyzed,finally 10-level 1.5 bit and 2 bit flash architecture are proposed.The key modules of the system are analyzed in more detail and the performance parameters are calculated in more detail.A bootstrap switch is proposed with reduced channel charge injection.Different from the traditional bootstrap switch,the bootstrap switch proposed in this thesis uses both NMOS transistor and PMOS transistor as the switch,increasing the gate voltage of NMOS to VIN+VDD and reducing the gate voltage of PMOS to VIN-VDD.Using the complementary characteristics of transistors,on the one hand,the influence of channel charge injection effect is reduced,on the other hand,the on resistance is reduced.Simulation results show that the proposed bootstrap switch can obtain better Spurious Free Dynamic Range and improve linear performance.The circuit is designed and simulated with Cadence Virtuoso software,and the chip is tested in the lab.When the clock signal is 25 MHz and the input signal frequency is1.17 MHz,the SNDR is 70.5 d B and the ENOB of ADC is 11.41 bit.When the input signal frequency is 12.21 MHz(close to Nyquist sampling frequency),its SNDR is 65.7 d B and the ENOB of ADC is 10.62 bit.During the circuit test,some problems in the circuit layout are found.After the circuit is improved,when the input signal frequency is 1.46 MHz,the ENOB of ADC is 10.85 bit and the SNDR is 67.1 d B.The range of DNL is-1LSB ?1.51 LSB,INL is-2.06 LSB ? 1.07 LSB.The average current generated during system conversion is 32.38 m A,and the average power consumption of the whole system during data conversion is 58.28 m W.This thesis also proposes a new low-power operational amplifier to replace the operational amplifier in the 6th to 10 th stages of the original ADC,and designs the second Pipeline ADC.When the input signal frequency is 1.46 MHz,the ENOB of the ADC is11.02 and the SNDR is 68.1.The range of DNL is-1LSB? 0.73 LSB,and the INL is-1.08 LSB ? 0.96 LSB.The linearity has been improved to a certain extent.The average power consumption generated by the system is 32.69 MW,which is 25.59 m W lower than that of the first version.The performance of Pipeline ADC meets the requirements of analog-to-digital converter in speed,accuracy and power consumption in narrowband Internet of things.