Research Of Low-Power-Consumption, High-Speed ADC For The SOC Application

As one of the crucial modules in video system like HDTV, analog-to-digital converter (ADC) realizes the signal conversion from analog to digital. Due to performance, power-consumption, reliability, cost and market-need, research of low-power-consumption, high-speed ADC for the SOC application has become an important topic in the filed of analog IC. To provide a re-useable IP for HDTV, the research is devoted to the designing of two 10bit ADCs with the 50MS/s and 100MS/s conversion rate respectively.A 10-bit 50MS/s CMOS pipeline A/D converter is implemented in 1.8V, 0.18μm CMOS process. Circuit techniques used to achieve low power-consumption includes dynamic comparator, optimal capacitor and OTA. Resetting T/H and stage circuit is adopted to cancel offset of OTA. Non-dominant pole of OTA is optimized to make OTA working stable. Measured performance includes a DNL of -0.6~0.7LSB, an INL of ±1.8LSB, and a SINAD of 44.9dB with 5.1MHz input at 50 MSample/s conversion rate. The ADC, with 57.6mW power-consumption and 1.15mW/MHz power-consumption/conversion-rate, occupies a core area of 0.52mm~2. No missing code is found during the test. Except that the SINAD is inferior to ADI current low-power-consumpiton product, which is due to the limitation of test equipment, DNL and INL is similar while the power-consumption and power-consumption/conversion-rate is improved a bit.Furthermore, based on the 50MS/s pipeline ADC, a 10bit, 100MS/s parallel ADC is completed, which is now in fabrication. The 100MS/s ADC is composed of two pipeline ADC with the conversation-rate of 50MS/s each. OTA sharing and all the low-power-consumption technique used in 50MS/s is adopted to lower power consumption. Two-stage sampling and digital filtering is used to correct the mismatch beweeen two pipeline ADC. Simulation result shows that the 100MS/s ADC works fluently, with the state-of-the-art power-consumption (57.6mW) and power-consumption/conversion-rate (1.15mW/MHz).