The Research And Design Of High Performance Low Power SAR ADC

With the development of deep submicron technology,many functional circuits are replaced by digital circuits.Currently,the system on chip(SOC)which is mainstream is mainly composed by digital circuit.Digital circuit is easier to design and has strong anti-interference ability,but it can only deal with digital signal.However,signals from nature such as light,air pressure,magnetic are analog signals,which are continuous all the time.Only by transforming analog signal to discrete signal by Analog-to-Digital converter(ADC),then digital circuit can deal with the signals from nature.As the link between the analog and digital world,ADC must satisfy market demand from its accuracy,speed and power consumption.Currently,the fifth generation communi-cation technology is developing and driving the development of all kinds of new products,such as smart wearing,smart furniture,etc.These new products need an ADC with a faster switching speed and a lower power consumption to increase the battery life.Among numerous ADSs,Successive approximation register ADC(SAR)is widely used for the reason that it has simple structure,low power consumption and the ability to be compatible with advanced technology.The aim of this paper is to design a 12 bit 10MS/s SAR ADC with lower power consumption and higher performance.The main research and innovation of this paper are as follow:1)According to the research of digital-analog converter(DAC),a split-bridge DAC was designed.This kind of structure is the combine the split DAC and bridge DAC,so it has two advantage:(1)The structure saves 12.5% average power compared the bridge DAC.(2)While the DAC is working,differential output's common mode voltage is constant.2)Based on the study of the MOS switch,optimize the bootstrapped switch in the sample hold circuit.By modifying the switch mos' s substrate,the switch mos' s threshold voltage in bootstrapped is constant while the input voltage changes.Under the same conditions,the ENOB of improved bootstrapped has improve 1.755-bit.3)The design uses the pre-amplifier comparator to reduce the transmission time.And proposes a calibration solution by calibrate the parasitic capacitance between the amplifier and latch.Compared to traditional comparator offset voltage calibration,this solution does not require high performance amplifier,reducing power cousumption and design difficulty.By proposed calibration,the offset of the comparator drops from 10.6mV to 147.24 uV.The propose offset calibration work before the SAR ADC work,so it save the calibration time during the comparison.The design and simulation of SAR ADC is completed by technology TSMC180 nm and software Cadence IC616 through transistor to layout.According to backend simulation,with the 10MS/s sampling frequency,the proposed SAR ADC's SNDR is 64.05,the SFDR is 73.7dB,the ENOB is 10.35 bit and the FOM is 32.57 fJ/conv-step.