| With the development of communication systems,various applications have higher and higher requirements for communication systems and this puts forward further requirements for the accuracy,speed and power consumption of analog-to-digital converters（ADC）.For example,the 77 GHz FMCW millimeter-wave radar wireless communication system generally requires the ADC to achieve a sampling rate of more than 20 MHz and the SNR needs to reach more than 60 dB;the WiFi 6E wireless communication system generally requires the ADC to achieve a sampling rate of more than 320 MHz and the SNR needs to reach more than 45 dB;UWB Ultra-wideband wireless communication systems generally require ADC sampling rates above 500 MHz and the SNR needs to reach more than 38 dB.In response to the above requirements,this paper studies and designs medium-speed,high-speed and ultra-high-speed ADCs.The main contents are as follows:（1）Aiming at the requirements of FMCW millimeter wave radar wireless communication system,this paper studies and designs a 30 MS/s 12bit SAR ADC.Asynchronous timing design is adopted inside the chip and bootstrap CMOS complementary switch is used to reduce the nonlinear effect caused by charge injection and improve the sampling linearity.A high-speed dynamic comparator is designed.In view of the problem of offset voltage,a foreground calibration circuit is designed to calibrate by controlling the substrate voltage of the input transistor.Monte Carlo simulation results show that after calibration,the offset voltage drops to the range of-0.3～0.43 m V.A non-binary capacitor array structure with redundancy is designed,which reduces the requirement of voltage establishment accuracy during high-level switching.The chip adopts 55 nm CMOS process.The test results show that the power consumption of ADC is 0.92 m W under 1.2 V power supply voltage,SNDR is 58.05dB,SFDR is 60.51 dB and ADC FOMW is 46.9 fJ/cs under 9.873 MHz input condition.（2）Aiming at the requirements of WiFi 6E wireless communication system,this paper studies and designs a 10 bit 400 MS/s 2b/cycle high-speed SAR ADC.By characterizing the difference between the input voltages of the comparator in the time domain,a new 2b/cycle structure is proposed which reduces the quantization period by half compared with the traditional SAR and improves the working speed.An improved low-power 2b/cycle capacitor switching timing is designed which can reduce the switching timing power consumption by 50%compared with the traditional Vcm timing.A control logic parallel to decoding and DAC switching is designed to reduce the loop delay and improve the speed of the control logic.The core layout area of the chip is 378μm×348μm.The post-simulation results show that when the input frequency is199.609 MHz,the ADC output SNDR is 56.6 dB,the SFDR is 71 dB,the power consumption of the ADC core circuit is 6.7 m W.The power consumption efficiency FOMW is 30.1 fJ/cs.（3）Aiming at the needs of ultra-wideband UWB wireless communication systems,this paper studies and designs a single-channel ultra-high-speed 8 bit 800 MS/s two-stage Pipeline time-domain Flash ADC.In the aspect of circuit,aiming at the linearity problem of traditional voltage time converter,a high linearity voltage time conversion circuit is designed and the output SNR up to 61.4 dB.A time digital converter with high time resolution is designed by using 4 times time interpolation technology to reduce the gain requirement of the voltage-time converter.A high-speed dynamic residual amplifier is designed between the two stages to amplify and transmit twice the residual voltage and the output SNR is 60.9 dB.The core circuit area of the chip is 370μm×180μm.The post-simulation results show that at 25°C TT process when inputting399.21875 MHz,the ADC output SNDR is 47 dB,SFDR is 62 dB,the power consumption of the ADC core circuit is 8.05 m W.The power consumption efficiency FOMW is 54.8 fJ/cs. |
