Research And Design Of12-Bit Asynchronous SAR ADC

Compared with other types of analog-to-digital converters,Successive Approximation Register analog-to-digital converters(SAR ADCs)own low power consumption,high accuracy,and simple structure,and are widely used in sensor networking,biomedicine,video processing,and wireless communications.However,the traditional charge redistribution SAR ADC has problems such as high hardware consumption and low energy efficiency during the conversion process,so reducing the hardware consumption of SAR ADCs and improving their conversion energy efficiency has always been a key research topic.In this paper,the working principle,hardware consumption and energy efficiency during the conversion process of traditional SAR ADC are analyzed,and a capacitor switching switching strategy is studied,which reduces the hardware consumption of traditional SAR ADC and improves the energy efficiency of the conversion process of SAR ADC.Based on this switching strategy,this paper designs a 12-bit asynchronous SAR ADC with 5MS/s sampling rate,which is different from the traditional SAR ADC and has the following characteristics:1.The weight of the base plate is connected to the positive half of the capacitance,and the weight of the other half of the base plate is connected to the reference voltage.Therefore,the backplane of the weighted capacitor during the sampling process is equivalent to the input common-mode level(V_cm(half of the supply voltage(V_DD),eliminating the(V_cm generation and buffer circuitry,and reducing the hardware consumption of the circuit.2.The SAR ADC designed in this paper makes a direct comparison after sampling to obtain the digital output of the most significant bit,which replaces the setting operation after sampling of the traditional SAR ADC.It only needs 11 bit capacitor DAC to realize the 12 bit precision SAR ADC.As the overall capacitance consumption of SAR ADC is exponentially related to the number of bits of ADC,for high-precision SAR ADC,the chip area occupied by capacitance will increase significantly,resulting in reduced circuit speed and increased power consumption.Therefore,the 12 bit SAR ADC designed in this paper adopts the 6+5 segmented capacitor array structure based on the charge redistribution principle.Compared with the traditional 6+6 segmented capacitor array SAR ADC,the capacitance consumption of this design is reduced by 25%,and the hardware consumption of the circuit is further reduced.3.In the conversion process,the SAR ADC designed in this paper only charges and discharges the current weight bit capacitor,and does not need to charge and discharge the previous weight bit capacitor,which improves the energy efficiency in the conversion process.4.The circuit and layout are designed under SMIC 110nm process,and the core layout size is 487?m×173?m.The post simulation results show that under the condition of 1.2V power supply voltage and 5ms/s sampling rate and near Nyquist frequency input,the ENOB is 11.48bit,the SFDR is 71.48d B and the SNR is 71.29d B,which meets the expected design index.