Research And Design Of A 12-bit SAR ADC

As the bridge between analog system and digital processing system, analog to digital converter(ADC) plays a crucial role in most of today's electronics applications, such as wireless sensor networks, industrial monitoring and data acquisition. Compared with other types of ADCs, successive approximation register(SAR) ADC, with moderate to high resolution, moderate speed, low power consumption, and small area characteristics, is more suitable for system on chip(SoC) applications.Following the top-down design method, a 12-bit SAR ADC for SoC is exploited in this thesis. The work is designed and fabricated in SMIC 0.13 ?m CMOS process, using the fully differential C-R hybrid digital to analog converter(DAC) structure. Scaling capacitor is adopted to improve the precision and reduce the chip area. Through the optimization of placement and routing, the DAC achieves high precision. The error existing in the DAC is analyzed in detail, and self-calibration technique is researched to minimize the error.Besides, a multi-stage comparator is designed, and an offset calibration technique with capacitors is applied. The structure of non-redundant SAR with only one set of registers allows area optimization and minor code probability error.The measurement results show that the effective number of bits(ENOB) of this ADC reaches 9.711 bit at Nyquist frequency with 0.83 MHz sampling frequency and the total current of the ADC is 970 ?A with a 3.3 V power supply. As the clock frequency changes,the ADC has a reliable performance with ENOB of 9.7 bit from 1.5625 MHz to 16 MHz,which means a sampling rate varying from 0.104 MS/s to 1.07 MS/s. This SAR ADC can increase the integration of system and reduce the cost with the consideration on the signal integrity.