10-bit High Precision Low Power SAR ADC Design Research

SAR(Successive-Approximation-Register)ADC, which has moderate accuracy and speed of transform, can insure to get a low power and small chip size under CMOS manufacturing process. It has a trade-off among speed, accuracy, power consumption, and cost, comparing with high-precision Σ-ΔΔDC and Flash ADC, which makes it have more widely application area.Nowadays, as ultra-low voltage circuit has a ultra-low power consumption, its design attracts a massive attention. It’ll be used in wireless sensor network in the future finally. Because of the trade-off between speed and accuracy of SAR, it becomes the best choice in moderate transform speed and low power but high accuracy signal processing application.That is why this topic is chosen,"10-bit High Accuracy Low Power SAR ADC Design Research ". the main purpose is to study how to improve the accuracy of transform though decreasing the mismatch of capacitance, and increasing valid bits, at the same time reduce the power consumption and decrease the chip size..The charge scalling type DAC using binary weighted capacitor array charge redistribution, to accomplish the digital-analog conversion process. It has a high transfer speed, and can work under only one reference voltage. But with the increase of bits, value and number of the capacitors will increase more, which will reduce the speed and occupy a lager area. At the same time, the mismatch error of capacitance will lead to nonlinear error and affect the precision. Therefore, the improved capacitor array structure is put forward. In segmented structure, the capacitors are divided into two parts of upper and lower bits, which greatly reduces the number of capacitors, thereby reducing the area. At the same time, because of amplifier’s high gain and negative feedback, the input node is equal to a virtual ground. So it can eliminating the nonlinear, and also the mismatch.For a mixed-signal SOC Integrated circuit design, the stage of layout design is also important. In this paper, a series of methods is put forward to optimize the performance of this ADC. For instance, centrosymmetric structure, isolation between analog&digital block, guard ring and so on. These all make contribution to improve immunity, and reduce noise, to make the chip be robust.The design of10-bit mixed-signal SAR-ADC is based on SMIC0.35um mixed-CMOS process. It works in a3.3v power supply, with clk frequency200KHz. The power consumption is about5mW. Cadence EDA tools are using for layout design. the final chip size is1600*1350(um2). This chip is already taped out for application in the future.