A digital calibration technique for14-bit400MS/s current steering DAC is presented. Under calibration module, the block acts as thermo decoder, and generates a calibrated clock to control the switch array to calibrate each current source. Single frequency clock can cause a repeating pattern of errors that appears as spurious tones, leading to low performance. A random clock based on LFSR and CA is introduced to convert the spurs into noise. The circuit has been designed and implemented in SMIC0.18μm CMOS1P6M process. The supply voltage is1.8V. The final results indicate that this calibration technique improves SFDR up to18dB, when input5MHz signal at200MHz. That research shows this technique could improve SFDR and be used in high-resolution current steering DAC. |