Design And Implementation Of Two-speed SerDes Chip

With the rapid development of technologies such as 5G,big data,and artificial intelligence,applications such as autonomous driving,virtual reality,and short video have entered people's lives,affecting people's work and lifestyle.Behind these technologies and applications all rely on communication equipment to transmit massive amounts of data at a high speed,and with the continuous enrichment of applications and the continuous growth of the amount of data,higher requirements for data transmission rates will continue to be put forward,which will force people to A never-ending exploration of high-speed data transfer technologies.SerDes,as the mainstream technology of high-speed serial transmission,was first used in the field of optical fiber communication,and now it has been widely used in the interfaces of various communication and computing devices,and has become the physical layer implementation scheme of many communication protocols.SerDes is the abbreviation of serializer/deserializer.It includes independent transmit channel and receive channel.The transmitting channel generally includes an encoder,a serializer,and a low-voltage differential signal transmitter,while the receiving channel generally includes a clock data recovery circuit,a deserializer,and a decoder.Since SerDes uses low-voltage differential signals for transmission,the data has strong anti-interference ability,and can support large data transmission rates and long transmission distances.Thesis completes the digital module design of a high-speed SerDes interface chip with a data bandwidth of up to 2.6Gbps.The chip has two speed modes,full-speed and half-speed,and supports Ethernet IDLE sequence correction and Fibre Channel EOF sequence correction.Based on the FPGA,the function test and bit error rate estimation are carried out on the chip that has been taped out.Thesis first briefly outlines several commonly used SerDes interface chip architectures,then elaborates on the 8b/10b coding principle,and then introduces the general structure of the 8b/10b SerDes interface chip,including structural composition,function of each module,data flow It also briefly outlines the structure and function of three important analog circuits in SerDes:PLL,LVDS,and CDR.Then,three test methods of SerDes interface chip are introduced,which are direct test by ATE,test system built by FPGA,and on-chip test by built-in self-test.Rate,jitter,and eye diagrams are introduced.Next,Thesis describes in detail the structure of the designed dual-speed SerDes interface chip and the functional principle and design method of each digital module.These digital modules include 8b/10b codec,Comma detector,Ethernet IDLE sequence correction module,Fibre Channel EOF sequence correction module and two-speed switching module.Finally,using the SOPC design method,a functional test system is built on the FPGA to perform the software-hardware collaborative functional test and the bit error rate estimation for the chip that has been tape-out.The results show that the dual-speed SerDes interface chip works in three working modes.can operate normally,and the estimated bit error rate is less than 10^-7.