Font Size: a A A

Multifunction Network Tester And FPGA Implementation Of Its Partial Modules

Posted on:2012-10-06Degree:MasterType:Thesis
Country:ChinaCandidate:F HeFull Text:PDF
GTID:2248330395485865Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
With the continual growing of the Internet industry, the network infrastructure and its application fields expand continuously. The network testers are the essential facilities to develop the network equipments and operate or maintain the networks, resulting in a large network test equipments market. Currently, the network testers produced domestically can not fully satisfy the market due to their limited functionalities, while those bought from overseas are too expensive. Besides, China does not own all the core technologies in the development of network testers. Therefore, it is significant to develop China’s own network testers with independent intellectual property, multi-function, high integration, excellent performance and high performance price ratio as well. The development of China’s own network testers can promote the healthy development of our country’s network testing technologies and industry. It is expected that such a network tester would find wide applications.Sponsored by the subject of the Research&Development of a Multi-function Network Tester, this dissertation reviews the principles of SDH,10GE, ATM and the FPGA design technologies. Then we demonstrate the functions and performance of the multi-function network tester based on analyzing and comparing with the existing network testers. This dissertation proposes an implementation scheme of the multi-function network tester and its functional modules, followed by the design of its working procedure chart. The emphasis of this dissertation is on the detailed realization of the test data processor in the multi-function network tester, and the FPGA design and verification of the modules of the cell delay test, Packet over SDH level3(PoS3) interface and scheduling with VHDL programming. This dissertation also proposes a novel approach could be used in the multi-function network tester, including the network delay test, delay jitter calculation and test. A primary analysis of these methods has been made. Finally, we summarize the whole dissertation and provide some possible extensions for future work.
Keywords/Search Tags:Multi-function network tester, Test data processorVery high speed integrated circuit Hardware Description Language (VHDL)Field Programmable Gate Array (FPGA)Asynchronous Transfer Mode (ATM)
PDF Full Text Request
Related items