Design And Implementation Of SerDes Interface Test Modules

As an efficient communication technology,Serializer-Deserializer(SerDes)has gradually become the mainstream high-speed serial transmission technology under medium and long transmission distances occasions in recent years.Now SerDes technology has been widely used in high-speed communication systems in various fields,so the test results of SerDes interface chips play a crucial role in whether these chips can be put into use formally.Bit error rate(BER),jitter and jitter tolerance are several important indicators used to test the SerDes interface chips.Jitter and BER testing can be performed with instruments such as digital communications analyzers(DCA),oscilloscopes,and bit error rate testers(BERT).However,these kind of test equipment is often expensive and not portable.Therefore,it is very meaningful to study how to build a test system to test the key indicators in the process of SerDes interface data transmission.This subject is devoted to the research and development of a high-speed SerDes interface chip integrated test module based on FPGA,which completes the generation,transmission and reception analysis of multiple channels of high-speed test signals without the aid of external instruments.The main research contents of the subject include:1.Realization of high-speed serial signal transceiver function: The multi-channel high-speed serial test signal transceiver function of the test module is realized.It mainly includes the hardware circuit design of the test module,the realization of the high-speed data transmission rate adjustment function,the realization of the signal voltage swing adjustment function,the realization of the transmission signal pattern control and the realization of the transmission signal jitter injection.2.Realization of the BER eye diagram and its fast test algorithm: By calling the internal logic resources of the FPGA,the fast BER eye diagram analysis of the high-speed serial signal input at the Receiver(RX)can be realized.With these key measurement parameters of the eye diagram,the signal transmission quality of the SerDes interface chip can be evaluated.This part mainly consists of the realization of the BER eye diagram function module,including the design of the underlying hardware control process,the realization of the selection of key parameters of the eye diagram,and the realization of the fast test algorithm.3.Realization of serial transmission data BER and jitter tolerance test function: The realization of the high-speed data BER test function module and the design of its control flow have been completed.Based on the principle of jitter tolerance,the realization of the jitter tolerance test function of the interface under test is completed.The subject currently realizes high-precision adjustment of data transmission rate in the range of 0.5Gbps?32Gbps,supports PRBS pattern and custom pattern transmission,the signal jitter frequency is 40 k Hz?12.5MHz,the measurable signal amplitude of the eye diagram is 80 m V?840m V,the eye diagram amplitude is 80 m V?840m V,which has±20m V amplitude accuracy,and supports magnitude-settable BER test.