Design And Implementation Of An Integrated ATE Platform For High-speed Serdes Interface Testing

Under the guidance of Moore's Law,integrated circuit mostly develops towards the direction of high density,high speed and high reliability,and the data transmission requirements between circuits appear to be more and more important.Serial Serdes interface technology has gradually replaced parallel interface technology,which adopts differential data and embedded clock mode to greatly improve data transmission rate.Nowadays,it has been widely used in standard serial interfaces such as PCI-Express bus,100 GBASE Ethernet,and OIF-CEI backplane transmission.The interface transmission rate has reached 16Gbps~56Gbps,which brings many challenges to the test.The mainstream Automatic Test Equipment(ATE)in the market,although it has the characteristics of high integration and strong universality,it cannot meet the requirements of high-speed Serdes interface Test in the Test rate.As a result,the Serdes interface test of the chip mostly adopts "design-guaranteed" self-test,and the test of interface parameters and performance can only be limited to laboratory verification measurement.Therefore,in order to ensure high quality and high efficiency of Serdes interface full-speed test,it is necessary to build a new integrated and automated high-speed interface test platform.This paper combines the advantages of ATE test platform and high-speed measurement instrument(oscilloscope,error code tester,etc.),organically integrates the two,and realizes the integration and automation test platform for high-speed test of complex chips.Firstly,this paper studies the test technology of high-speed serial interface and puts forward the corresponding test requirements.Then,according to the test requirements and existing equipment,the hardware structure of the test platform was systematically constructed,and a special test load board was made.Then,the command control system and collaborative integration software of ATE and measuring instrument are designed comprehensively.Finally,a multi-device efficient and collaborative automated test system was formed,and the function and key parameters of the Serdes interface chip with a rate of 28 Gbps were tested.In this paper,a self-designed SOC/Serdes chip in China is taken as the center and demand analysis as the guide to carry out the specific system hardware architecture design,software programming,instantiation test and verification.Compared with common test solutions,the collaborative integration test platform designed in this paper provides a more effective solution to the test requirements of high-speed interface automation,high quality and high coverage.At the same time,it is of great practical value in the initial test,small andmedium-sized test or identification test of chip products,which ensures the test traceability and improves the accuracy of the test.