Research On Test Method Of 10.3125Gbps High-speed SERDES Chip

With the continuous development of science and technology,the data transmission rate between chips and modules within a system continues to improve,and the Serializer / Deserializer(SerDes)technology develops at an increasing pace and receives more attention.But with the acceleration of the transmission rate,the stability of the SERDES system becomes a more crucial concern.In order to ensure the stable operation of the SERDES system,it is increasingly important to detect various possible problems.The idea of Design For Test(DFT)is developed to ensure the completion of problem testing without incurring too much cost.The idea is to include in the chips a circuit module dedicated to testing.Such dedicated circuit modules are called DFT.The biggest advantage of DFT is to diagnose potential problems with the chip with minimum cost and highest efficiency.This paper focuses on the practicality of two test methods in DFT: the AC-Boundary Scan and BIST.Through the AC-Boundary Scan,the connectivity between the modules in the SERDES system is tested to detect any disconnection in each path.BIST tests the logic of various paths in the SERDES system to ensure that each path has a good working condition.This paper also carries out eye diagram tests on the quality of the signal transmitted in the data transmission channel of SERDES in the board level test,with particular focus on whether the inter-symbol interference of the transmission signal is kept within a reasonable range.The eye diagram tests monitor the signal quality of the transmission in order to provide an important reference for subsequent design and modification of the circuit.Finally,eye diagram tests have very high demands for the performance of the oscilloscope,which causes the cost of such oscilloscopes to be very high.Also,during the testing process,the use of probes in the tested circuit introduces unnecessary changes in the load,among other problems.At the end of this paper,the author proposes a test method of on-chip high-speed signal jitter in order to avoid the aforementioned unavoidable shortcomings of traditional eye diagram testing.The main idea of the proposed test is to test the jitter of the signal directly from the inside of the system without introducing an external oscilloscope.Through a dedicated test module within the system,the method directly detects the signal jitter.And the test results are converted to binary data sets that are easy to analyze and store in order to provide reference for future design improvements.In this paper,the research findings on the multiple test methods for the 10.3125 Gbps high-speed SERDES chip should significantly help improve future testability design for chips.