For 10bit The 100msps Pipelined Adc Sub-adc Research And Design,

The increasing digitalization in all spheres of electronics applications, from telecommunication systems to consumer electronic appliances, requires high performance analog-to-digital converter (ADC). Based on the research and analysis of system structure of 10-bit 100MSPS Pipelined CMOS ADC, according to the system performance, the specifications of sub_ADC is obtained, while the sub_ADC including the preamplifier-latch comparator, the reference ladder resistance and the clock-control encode circuits are discussed in detail.Firstly, based on the analysis of the pipelined ADC which consists of a 2.5-bit first stage followed by five 1.5 bits/stage and finally the pipeline is terminated with a 3-bit flash sub_ADC, and in terms of the demands of ADC system, sub_ADC's specifications are discussed.Secondly, compared with some other kinds of comparator structure and based on the Preamplifier-latch fast-compare theory, a novel topology of CMOS preamplifier latch comparator circuit is presented. Considering trade-off between kickback noise and power dissipation, reference resistance value is optimized. According to the encode demands of different stage resolution, clock-control encode circuit is designed. In practical design, not only nonideal factors from noise, mismatch, offset etc. are taken into consideration, but also the desired sub_ADC performance is achieved with reduced power dissipation.Thirdly, sub_ADC has been simulated by Cadence EDA software with standard SMIC 0.35μm/3.3V Si CMOS process model. From the simulation results, we can see that, for the presented CMOS preamplifier-latch comparator, its transfer delay time is 231ps, and the power dissipation is 118.6μW. For the different stage resolution sub_ADC with the comparators, it is shown that all sub_ADC work right at clock frequency up to 100MHz with a total power dissipation of 5.57mW, while minimal resolution voltage is 10mV, settling time less than 1.2ns. When the optimum value of ladder resistance is 1KΩ, the glitches introduced to input signal and the reference...