.3 G Receivers Adc Sub-unit Design And Error Correction Method

As the rapid development of communications technology and digital signal processing technology, Analog-to-Digital Converters have been widely used because they are the interface between analog signal and digital signal. In a large number of ADC structures, pipelined ADCs are the most suitable for communication system equipments according to the characteristics of communication system applications. Because pipelined ADCs have a very good compromise between resolution and speed, and relatively low power consumption, it is suitable for portable communication system equipments.In this paper, the cell circuit, sub-ADC, for the pipelined ADC with 14b and 100MSample/s has been designed, and a background correction algorithm used to remove the DAC static noise in the first two stages has been proposed. The main contents include the following:Firstly, the basic working principle of pipelined ADC is analyzed. The final decision according to the system performance is that the first four stages are 3.5b and the last one is 2b, meanwhile performance indexes of every stage are defined, it's useful for specific sub-ADC designing.Secondly, the designing of the sub-ADC is divided into two parts, i.e. designing comparators array and designing high-speed digital coding circuit. According to the preamplifier-latch fast-compare theory, the eventual adoption of preamplifier latch comparator can meet the precision and speed of sub-ADC. Using clock-controlled current source can solve the problem of the high power consumption due to the high-precision. Inserting an isolation stage between the preamplifier and the latch can weaken the kickback noise's impact on the reference voltage. In accordance with the characteristics of the output code of the comparators array, programmable logic array (PLA) is employed rather than the traditional digital gate-level circuit while high-speed digital coding circuit is being designed. This can significantly improve the coding circuit speed. Based on the standard CMOS process, the simulation results of the sub-ADC show that it is designed in full compliance with system requirements. Thirdly, the simulation results of pipelined ADCs based on Matlab show that the static noise due to capacitor mismatch in the first two DACs impacts the system performance mostly. The SDEM (segmented DEM) technology is the improvement of the traditional DEM (dynamic element matching) technology and applied in the first two DAC, so that the static noise would be averaged, and then the averaged noise is removed from the system outputs by using the DDNC (digital DAC noise cancellation) technology. The Matlab-based simulation results show that the system improves the precision of 2.4b after removing the static noise in the first two DACs.