| The design of high-speed, high-resolution ADCs continues to present greater challenges as the device dimensions and supply voltages are scaled down. While generic issues such as capacitor mismatch provided the impetus for earlier calibration techniques, deep-submicron low-voltage technologies have made it increasingly difficult to realize high-gain op amps, requiring additional calibration that corrects for gain error and nonlinearity. With the declining intrinsic gain of transistors, it is expected that the notion of fast-settling, low-voltage, high-gain op amps will eventually become obsolete.;This research explores the use of low-gain op amps in high-performance pipelined ADCs. A new architecture incorporates a blind LMS calibration algorithm to correct for capacitor mismatches, residue gain error, and op amp nonlinearity. The calibration applies 128 levels and their perturbed values, computing 128 local errors across the input range and driving the mean square of these errors to zero. Fabricated in 90-nm digital CMOS technology, the ADC achieves a DNL of 0.78 LSB, an INL of 1.7 LSB, and an SNDR of 62 dB at an analog input frequency of 91 MHz while consuming 348 mW from a 1.2-V supply. |
