Research And Implementation Of High-speed Ser Des Interface Chip Testing Technology

High speed SerDes interface has become the main development direction of communication bus in the future because of its fast transmission speed,high reliability and simple connection.At present,the measurement of high-speed interfaces of many domestic circuits such as CPU,FPGA and DSP mostly adopts the way of self-test or board level verification guaranteed by design,which will bring the problems of insufficient characteristic parameter test and low test efficiency.Therefore,it is necessary to build an automatic test platform to meet the high-quality test of characteristic parameters of SerDes interface chip.This topic designs the Device Interface Board(DIB)and the test program required to test the high-speed SerDes interface chip,and completes the function verification of the chip and the consistency test of the jitter,eye diagram and other characteristic parameters of the high-speed interface in the Automatic Test Equipment(ATE).The specific research contents are as follows:(1)Research on SerDes test method.On the basis of ensuring the correct function of SerDes interface chip for data transmission,the test methods of common mode voltage,rise / fall time,jitter and other characteristic parameters are studied,and the test program is designed by searching the value to test the interface parameters.(2)Overall test scheme design.The basic principle of high-speed SerDes interface chip is studied.Combined with the automatic test system,the specific test scheme based on ATE serial loop is determined to solve the problem of low efficiency of high-speed interface test.According to the test requirements,the automatic test process is designed to complete the functional verification of the chip to be tested and the test of key parameters.(3)Test platform construction and hardware design.The PRBS generation circuit is designed to send the test vector and the bit error rate detection circuit to judge the output response.Analyze the digital channel demand and power supply demand of the circuit to be tested,determine the board resources required by ATE,design a good DIB board,analyze the loss of the DIB board and carry out simulation verification to ensure the signal integrity of the high-speed channel of the DIB board.(4)The results are analyzed and verified.Design and debug the test program based on CTC2118 So C products,analyze the test results and verify the feasibility of the design scheme.This paper designs a test scheme of SerDes interface based on ATE,and completes the hardware design,software test program design and function verification test of the test platform.The physical layer parameters of the high-speed SerDes interface chip with the maximum transmission rate of 5Gbps and the maximum data throughput of25 Gbps are tested,and the test results are consistent with the measurement results of the standard instrument.