DFT Integrated Design And Test On ATE For SerDes Circuit

As a mixed analog-digital and high-speed circuit, SerDes is often integrated in theIP core of PCIE and SATA. Test in mixed analog-digital circuits is difficult, the teststimulus generation, response analysis, and test coverage are the focus of the study.When an IP core is integrated into the chip, its own input and output ports are embeddedin the chip, so the ports with testability lost its original controllability and observability,also become untestable.In an integrated design, how to access the internal test circuits ofIP cores by using the chip’s pins as little as possible is necessary to be solved as a keyproblem.The test of high-speed signals bring about challenges to the Automatic TestEquipment (ATE) and the design of test board (loadboard).This paper is based on ATE, research has been done in DFT integrated design andtest of SerDes circuit in IP cores of PCIE and SATA. The main work of this paper is:i. The clock structures and functional modules of Serial interface circuit ofPCIE and SATA which can reach high-speed data rates have beenanalysed,the principle of SerDes circuit has been elabroted.ii. Based on the IEEE1500standard,the analysis of design for testability ofthe SerDes circuit of PCIE andSATA is done,much more analysis of TAPcontroller, test wrapper and the design of loopback testing circuit havebeen done.Timing diagram describes the principle of dedicated JTAGinstructions-CRSEL. For the interface of PCIE and SATA,We design andverify the DFT circuit, complete ATPG generation and verification..iii. Based on93000tester,We develope a test plan for the interface circuits of PCIE and SATA,and design a loadboard,then complete the internal and external loopback tests. This research work not only provides convenience for the correct application of IP core in the integrated design,but also can be used for reference in the test of other IP cores. The test results show Verigy93000capable high-performance IP core testing.