Design And Implementation Of Bit Error Rate Test Module With Adjustable Edge Jitter

When the data transmission rate is very high,there will be a certain phase deviation between different bits of the parallel data,and there will be transmission delays between the buses,which will cause bit errors.Serial bus transmission can achieve longer-distance and higher-speed transmission,and is the preferred transmission method for high-speed communication.In high-speed serial communication systems,due to factors such as power supply noise,inter-symbol interference,and transmission channels,jittered serial data is transmitted through high-speed channels,which will have a significant impact on the entire system,so the high-speed serial communication system is improved.The receiver's jitter tolerance and clock data recovery capabilities are becoming more and more important.Therefore,in order to effectively test the jitter tolerance and clock data recovery of a high-speed serial communication system,a serial signal source with a certain amount of jitter is required,so jitter injection for high-speed serial signals is of great significance.This subject is devoted to the development of a bit error rate test module with adjustable edge jitter with a line rate of up to 32 Gbps.The output swing and pattern pattern can be adjusted,the output high-speed serial signal can be de-emphasized,the adjustable and controllable edge jitter can be injected,the bit error rate of some common pattern patterns can be measured,and the receiving high-speed serial signal can be measured Analyze the eye diagram and obtain the eye height,eye width and other parameters.The main research contents include:1.Research on jitter injection: This topic aims to inject adjustable and controllable edge jitter into high-speed serial signals.The jitter injection of high-speed serial signals is realized by injecting jitter into the high-speed output clock of the phase-locked loop that drives the parallel-serial conversion.Study the working principle of phase-locked loop and the law of jitter transfer to provide a theoretical basis for reference clock jitter transfer.Several methods for jitter injection to the input reference clock of the phase-locked loop are proposed.Research on the fine phase interpolation of the high-speed output clock of the phase-locked loop.The high-speed output clock of the phase-locked loop enters the high-speed serial transceiver sending module.The module has a built-in phase interpolator that can adjust the phase of the clock,and finally the phase jitter is synchronized to On high-speed signals,complete the injection of edge jitter.Compare the advantages and disadvantages of different jitter injection implementations.2.Research on high-speed serial signal output: study the working principle of high-speed serial transceivers,design the dynamic reconfiguration port control process,study the realization of dynamic adjustment of the output frequency of the module phase-locked loop,and realize the output pattern mode and output swing control.On the basis of phase interpolation,the control and adjustment of the output signal jitter are realized.3.Research on high-speed serial signal input: Research on the realization of high-speed signal serial analysis,including bit error rate measurement and eye diagram measurement.Research the measurement principle of bit error rate of some commonly used pattern patterns,the measurement principle of statistical eye diagram,and complete the design and verification of serial analysis.Finally,the paper gives the test results and analysis,the data rate range is500Mbps?32Gbps,the jitter frequency that can be injected is 40 k Hz?12.5MHz,and the maximum jitter amplitude that can be injected is 2UI.It shows that the module meets the relevant index requirements of the subject and can realize the jitter tolerance and CDR test of high-speed serial communication systems.