Design And Research Of High Speed Phase Locked Loop In10G SerDes

With the development of optical access network technology, the optical fiber isreplacing the copper based digital subscriber lines and the gobal access network hasbeen based on the passive optical network. The10G-EPON is one of the most popularsolutions for the next-generation optical access network because of its high-qualityhigh-speed low-cost and high-relability. As the physical layer of optical fibercommunication system，SerDes is to serialize or deserilaze the data transfered in theoptical fiber. PLL is the key module of the SerDes, and its function is to generatehigh-speed clock to convert the low-speed parallel data to serial data stream andproviding reference clock to the CDR of receiver.In recent years, there are many challenges in designing PLL with the rapiddevelopment of SerDes: High speed requires PLL working at high frequency; Low BERgives strict requirements to output jitter of PLL; The demand of monolithic solutionmakes the PLL design not only be compatible with standard CMOS process but also besatisfied with the system specification.The goal of this thesis is to design a fully intergrated PLL which can be satisfiedwith802.3av protocol based on SMIC0.13μm MS/RF1P8M CMOS process. And themain content of this study includes: bringing forward an optimized design method forlow jitter PLL: restrict the loop parameters with jitter and gain peaking。This methodcan decrease iterative times and optimize the output jitter, guiding for the design of PLLused as an inner chip clock generator.Then, according to the choiced loop parameters, adding a pre-charged module anda cascade current mirror to the traditional differential-input charge pump for the purposeof increasing the switching speed and matching accuracy. This thesis improvesquadrature voltage-controlled oscillator on changing place of couping transistors andcross-coupling transistors to decrease equivalent noise of couping transistor to theoutput, and optimize the phase noise of quadrature voltage-controlled oscillator.A low jitter PLL is designed based on the loop parameters choiced before and theimprovement of circuits. The simulation results show that the output frequency is 5.15625GHz, the random jitter rms value is less than0.62ps the deterministic jitter peakto peak value is less than8.8ps, the power consumption is15mW and the lock time isless than6.5us. Then the key module QVCO is taped out and tested, the test resultsshow that the tuning range is4.5GHz to5.4GHz, the output phase noise is-104.531dBc/Hz@1MHz, the jitter rms value is1ps in central frequency, the finalresults satisfied with the design target.