Research On The SRAM Based On The Novel HVTFET

SRAM(Static Random-Access Memory)is an important part of the integrated circuits and plays an important role in the CPU,MCU,FPGA and other chips.The feature of SRAM affects the performance of these chips.However,the optimization of SRAM is difficult.On the one hand,it is limited by the manufacturing process.With the reduction of the transistor size,defects are inevitably introduced in the process of the production,resulting in a decrease in the yield of SRAM.On the other hand,due to the limitations of the devices and the circuits,scaling down is difficult,even if the minimum size of the chip is reduced,the devices will suffer from the short-channel effects,the DIBL effects,the quantum effects,etc.Researches on the improvement of SRAM have been carried out from various ways,including the basic device,the circuit structure,the algorithm,etc.,and therefore,it is very meaningful to study SRAM.After understanding the development status and the working principle of SRAM,this thesis studies the nano-scale SRAM from two aspects,the circuit and the device by the means of TCAD simulation.In terms of the circuit,this thesis proposes a new 6-tube all-NMOS SRAM,and proposes its read-write operation process and the peripheral circuit structure.Then the Cadence Virtuous is used to build an SRAM simulation platform,based on the TSMC's 65 nm device library.The simulation verifies the feasibility of the new 6-tube all-NMOS SRAM and analyzes its advantages.In terms of the devices,according to the characteristics of the HVTFET,this thesis proposes a structure of a 6-tube all-NMOS SRAM based on the HVTFET,and proposes its manufacturing process.According to the structure of the circuit simulation,the SRAM structure is rationally optimized.The all-NMOS SRAM based on the HVTFET device is innovative in both device and circuit.The HVTFET device is a vertical three-dimensional device,and the channel length can be less than 7nm.The all-NMOS circuit is different from the CMOS SRAM and avoid the limitation brought by the PMOS.The final simulated 6-tube all-NMOS SRAM based on HVTFET has high data stability.Its unit area is smaller than that of the CMOS SRAM,and its integration level is high.The current of HVTFET SRAM to maintain the data is lower than that of the traditional NMOS SRAM and the CMOS SRAM,which means the low static power consumption.