Research On The Structure Of FinFET SRAM

With the scaling of the integrated circuit technology,there is a serious problem in parallel to improve the transistor speed,that is,the short channel effect.Due to the short channel effect,leakage power consumption does not reduce any more,but will increase.The current popular FinFET structure can greatly reduce the impact of short channel effect and is mainly used in the memories.The static random access memory is a very important part in the SoC system.However,the 6T SRAM unit probably fail to read data successfully,and the read and write stability is very low and at the same time leakage current is so large.So the dissertation first analyzes several other SRAM units' advantages and disadvantages besides the 6T SRAM,and then study the four kinds of SRAM topology which are representative on the performance parameters.A conclusion is drawn that the performance parameters obtained by the FinFET SRAM are better than plane CMOS SRAM,and at the same time,according to the law a new 8T FinFET SRAM topology is presented.The 8T SRAM unit using the read port isolation design ideas,can effectively improve the read noise margin,which is short of RNM.The design idea of transmission gate is used to improve the threshold of write operation and reduce the write delay.Atthe same time,its average dynamic power consumption in the four SRAM structure is the smallest,and it is reduced by nearly 50%compared to the classical 6T SRAM,and far less than the classical 8T SRAM.In addition,the leakage current is also the smallest in the four SRAM cells.The new 8T SRAM unit can be used in the case of low latency requirements.