Research And Design Of High Performance And Low Power SRAM Based On Ultra Deep Submicron

With the rapid development and mutual integration of physics,materials science,engineering design technology,through interdisciplinary cooperation,people have made the minimum size of integrated circuits continue to break the restrictions caused by various factors in the original process,allowing the scale of integrated circuits getting bigger and bigger.In particular,in modern integrated circuits,memory circuits occupy a relatively large proportion.In the memory circuit,the static random access memory(SRAM)occupies an important position because it has the outstanding characteristics of not needing to be refreshed,being fast,and easy to use.Today,with the advancement of technology,SRAM has achieved rapid development.Although the reduction in process size is beneficial to the expansion of the use of SRAM,it also places stricter requirements on SRAM performance.Among them,the speed,power consumption and stability of SRAM are the top priorities.Therefore,designers need to consider various factors when designing SRAM.In order to solve the problem of reducing the power consumption of SRAM while designing to meet the requirements of high performance under advanced technology,based on the needs of engineering projects,this master thesis first starts with a summary of the development background and research status of SRAM at home and abroad,combining The solution to the development trend of SRAM is to design a fully customized 35*2048 SRAM with high performance and low power consumption that adopts the FinFET process.The specific work of this master thesis is to complete the following design: memory cell array layout,sensitive amplifier and precharge circuit design,address decoding circuit design,ELAT circuit design,read and write circuit design,redundant repair circuit design and the overall circuit and layout design.The innovations of this master thesis are:(a)In terms of circuits,gated clocks and static circuits are used as much as possible,and hierarchical decoding is used to reduce decoding delay and power consumption and ELAT control signal static to dynamic design reduces invalid clocks,It also improves the read and write circuit of the sensitive amplifier and SRAM,and additionally adds a redundant repair module to ensure chip yield;(b)in terms of layout,based on the design requirements of the FinFET process,the overall design layout is reasonably planned,and the sensitive amplifier Layout design optimization.After the overall design is completed,it is verified by DRC and LVS,and simulated by Hspice and redhawk.Because of the superiority of this fully customized,the read speed and power consumption are compared with the SRAM IP core MC array used in the project to demonstrate the correctness of the design and the design method to achieve the high performance and low power consumption goal.Specifically,in terms of high performance,this design achieves the design goal of accessing the frequency of 2.5 GHz,and the readout delay is about 20% faster than the MC array.In terms of low power consumption,while the performance of this design is far superior to the MC array,the power consumption is at the same level as the MC array,which achieves the purpose of low power consumption and highlights the advantages of full customization.This master thesis aims to provide a feasible reference solution for other people's design work in the future.