| Microprocessor is the core of System-on-Chip, and its low power design isimportant to the whole system. Meanwhile, the design of low power On-chip memorysystem is one of the most important research areas, due to more than60％energy isconsumed by the on chip memory system in microprocessor.This paper presents the new SRAM cell, its data read operation has a highstability, and compared with the traditional four and six SRAM cell, this kind ofSRAM cell has a higher static noise margin. Meanwhile, it make up two defects existin conventional SRAM. The new7T SRAM cell is consisted of two separate dataaccess mechanisms; one is for the read operation and another is for the write one. Inparticular, the design of our SRAM cell does not disturb the storage node during thereading operation. The SRAM cell is simulated in0.18μm CMOS technology. TheRead SNM is as high as1.43V at VDD=1.8V. It is found that the Read SNM issignificantly enhanced by1.6X and0.31X as compared to the conventional4T and6TSRAM cell respectively.This paper also presents the One-Bit Tag I-Cache for the purpose of Low powerconsumption. On-chip instruction cache is a potential power hungry component inembedded systems due to its large chip area and high access-frequency. Aiming atreducing power consumption of the on-chip cache, this paper propose a One-Bit TagI-Cache, where the cache size is judiciously reduced and the cache tag field onlycontains the least significant bit of the full-tag. this paper develop a cache operationalcontrol scheme for One-Bit Tag I-Cache so that with the one-bit cache tag, theprogram locality can still be efficiently exploited. For applications where most of thememory accesses are localized, One-Bit Tag I-Cache can achieve similar performanceas a traditional full-tag cache; however, the power consumption of the cache can besignificantly reduced due to the much smaller cache size, narrower tag array (just onebit), and tinier tag comparison circuit being used. |
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