Novel SRAM Cell Design In 65nm CMOS Process

High in reliability, fast in access and compatible with logic circuits, the Static Random Access Memory (SRAM) takes a great important position in the high-performance microprocessors and System On Chip (SOC). So it has a great significance to research the SRAM storage cell.In the paper, low power consumption, high in reliability and good ability to read and write are our design goals. We propose a new structure of 12T SRAM cell, compared with traditional cell, the new structure not only increases WM, enlarges RNM but also solves half select problem. Main research work of the paper are as follows:Firstly, we research the traditional 6T,4T,7T and 8T storage cells, and analyze their principle of read, write and hold status, and compared their performance with each other. At the same time we explain the reasons of differences in performance from the structure.Secondly, due to scaled technologies, reduced voltage and the increasing storage capacity, the soft error rate of SRAM cell become increasingly higher. Bit interleaving techniques is widely used to solve the soft error problem in the design of SRAM storage array, however, it will bring half select problem. The paper explains what is the half select problem as well as the new 12T cell how to solve it.Last, simulation results show that the proposed scheme has 0.4xhigher write margin (WM) and 1.3×higher read noise margin (RNM) than that of conventional 6T cell in a standard 65nm/1.2V CMOS process. Compared with conventional 6T cell, the dynamic read and write power consumption of total 128 cells reduce 81.3% and 88.2% respectively when MUX is 4.