Low Power And High Stability 8T SRAM Cell Design

As the CMOS process technology is continuing scaling, SRAM cell is more and more susceptive to the increased process variation. And the low supply voltage technology is also used for low power application. Both scaling technology and low supply voltage technology can reduce the stability of SRAM cell. At the same time, smaller transistors lead to increasing leakage,so static power is becoming an important source of power. It's predicted that on chip SRAM arrays will occupy most of the number of transistors of the whole chip. Reducing leakage of SRAM cell is an effective way to reduce the whole chip's power.In a conventional 6T SRAM cell, in read operation, the data storage nodes are directly accessed through the access transistors connected to the bit lines. So the data is vulnerable to external noise during read operation. Moreover, voltage distribution between access transistors and inverters heightens the "0" voltage level. 7T SRAM cell aims at improving the stability of 6T SRAM cell. The data storage nodes are isolated from the bit lines, and the voltage distribution is eliminated, so 7T SRAM cell becomes more stable than 6T SRAM cell. However, as only one NMOS is used for write operation,7T SRAM cell's weak write capability is a critical problem.A new 8T SRAM cell is proposed to improve the 7T SRAM cell's write capability. An extra PMOS is added to cut off the feed back of the latch in write operation, so new data is easier to write in, therefore the write capability enhances significantly. 8T SRAM cell also has some other advantages. All of transistors in 8T SRAM are the same and minimum size,so the cell's area increases only a little. Dual VTH process technology can be employed to reduce the leakage and accelerate the read speed. After that, only one bit line needs to discharge in read and write operation, the dynamic power consumption reduces significantly. Compare with 6T SRAM cell, 8T SRAM cell has much better stability and smaller power.