The Research And Design Of A High-speed And Low-power SRAM In DSP

SRAM is a bridge between CPU and memory, which is also an important part of digital signal processor. While processing technique moves toward sub-micron and nano these years, the shrinking of characteristic size probabilizes faster access time and higher density of integration, and yet puts SRAM into big challenges. Performance improvement of SRAM becomes a bottleneck of the digital signal processor development.For the purpose of meeting demands of high speed and high stability in certain circumstances under condiction of sub-micron and nano, in this paper, an optimal 512×32bit SRAM with fast access time and high stability is designed under TSMC 0.18μm CMOS process.First, based on the research of SRAM operation theory, system architecture, together with memory array division and peripheral circuits arrangement, is presented according to design requirements. Further, for the given requirements, modified designs for the memory cell and peripheral circuits are proposed. For the memory cell design, a novel 9T SRAM cell whose structure separates read and write path to ensure high data stability is adoped. Then the reasonable sizes of the transistors in the 9T are worked out so as to achieve otherwise performances. For peripheral circuits design, emphases are considered differently based on their functions respectively. Delay model is study while designing decoder, and other factors like speed, cost and chip area are taken into account. A scheme of stage-devided decoder is chosen to fasten speed and lower power,then the sizes of output drivers on each stage are calculated. When the paper goes on to sense amplifier design, a current-voltage hybrid mood amplifier is proposed in this paper. Unlike other current amplifier, the proposed work gains high performances without being influenced by device mismatching.Followed the circuit design, the layout of the proposed 512×32bit SRAM circuit is accomplished, then pre and post-simulation of circuits is carried using comprehensive simulation method.The results show that the speed and power of the proposed SRAM memory meet the design requirements. Although the area increases by using 9T SRAM cell, with stability decreasing in sub-micron and nano, for certain devices with high demand of stability, the proposed SRAM in this paper is feasible.