A Design Of Low Power And High Stability 9T-SRAM Cell

Low power consumption and high stability have become two central topics in SRAM design. Various techniques have been implemented to minimize the power consumption. Among them, supply voltage scaling has significant impact on the total power dissipation of SRAM arrays. Since the dynamic power is a quadratic function of voltage, scaling the supply voltage can significantly reduce the dynamic power. And voltage scaling can also exponentially reduce the leakage current, thereby reducing the standby power of SRAM arrays. However, as the supply voltage is scaled, the stability of SRAM cell will be degraded. On the other hand, as the process technology is continuing scaling, the sensitivity of SRAM cell to process variation increases. The combined effect of the lower supply voltage along with the increased process variations may lead to increased memory failures. In a traditional 6T SRAM cell, there exist a conflict between read stability and write ability. Therefore, improving one factor must unavoidably impact the other. During the read operation, the internal storage nodes are directly accessed by external bit-lines through the access transistors, so the data is vulnerable to external noise. Moreover,6T SRAM cell has a voltage distribution problem between access transistors and pull-down transistors during the read mode. All of these lead to a poor stability of 6T SRAM cell.This paper first introduces the research background and significance, and briefly summarizes the classification and characteristics of memory, then based on the research status of low power and high stability SRAM at home and abroad in recent years, proposes the main research work of this paper. Secondly, the paper introduces and analyzes in detail the work principle of several structures of commonly used SRAM cell, also explains the advantages and disadvantages of them. In the end of this paper, a new 9T SRAM cell is proposed, which employs a single bit-line to perform the write and read operations. The proposed cell enhances the write ability by cutting off the feedback loop of the inverter pair, and improves the read stability by using a separate read port. Thus, this proposed 9T SRAM cell can eliminate the conflict of read stability and write ability in traditional 6T SRAM cell. Additionally, because the proposed cell using single bit-line to perform read and write operation, this can significantly reduce the read and write power consumption. The simulation results using the SMIC 65nm process show that the proposed 9T cell achieves 2.31 X read noise margin,41.35% write ability improvement,33.55% total power dissipation reduction when compared with a traditional 6T SRAM cell at supply voltage of 1.2V. To sum up, comparing with traditional 6T SRAM cell, the proposed 9T SRAM cell has much better read stability and write ability, lower power consumption.