Full Custom Design And Realization Of Static Random Access Memory IP Core

With the development of SOC design method based on IP core, the need of reconfigurable IP core increases. Because of SRAM with low power characteristic, Static Random Access Memory is the most common and important memory component in CPU and other electronic products. At present, SRAM complier can generate different capacity SRAM conveniently and quickly, but its performance can’t reach high-speed and low-power goal in high performance microprocessor. So, it is significant to design a low power and high speed SRAM by full custom design. For reducing design cost, the designed circuit module with reconfigurable characteristic is necessary.The proposed16Kb SRAM IP core with reconfigurable input and output data bitwidth is implemented in0.5μm CMOS process. The tructure design, circuit design, layout design, BIST design and IP modelingof IP core are finished, in the same time, the chip after taping out is verified. This SRAM with proposed reconfigurable decoder structure can input and output64bits and128bits data width without changing the design. The design idea guide complier design. Besides, this paper researches on low power the design method of SRAM complier which is based on H-tree structure and optimized a kind of current mode amplifier, its power consumption is only60%of Latch structure amplifier’s.In typical case that the work power supply is5V, the delay of writing data in SRAM is less than1.85ns and the delay of reading data is less than1.98ns. Under the condition of500MHz clock frequency, the average power consumption is39.55MW. Comparing with the SRAM generated by the memory compiler in the same process, the designed SRAM’s average power consumption reduces by12%, and the access time reduces by19%.